Datasheet

© 2009-2011 Microchip Technology Inc. DS22229D-page 17
MCP6401/1R/1U/2/4/6/7/9
4.0 APPLICATION INFORMATION
The MCP6401/1R/1U/2/4/6/7/9 family of op amps is
manufactured using Microchip’s state-of-the-art CMOS
process and is specifically designed for low-power,
high-precision applications.
4.1 Rail-to-Rail Input
4.1.1 PHASE REVERSAL
The MCP6401/1R/1U/2/4/6/7/9 op amps are designed
to prevent phase reversal when the input pins exceed
the supply voltages. Figure 2-33 shows the input
voltage exceeding the supply voltage with no phase
reversal.
4.1.2 INPUT VOLTAGE LIMITS
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the voltages at
the input pins (see Section 1.1 “Absolute Maximum
Ratings †”).
The ESD protection on the inputs can be depicted as
shown in Figure 4-1. This structure was chosen to
protect the input transistors against many (but not all)
over-voltage conditions, and to minimize the input bias
current (I
B
).
FIGURE 4-1: Simplified Analog Input ESD
Structures.
The input ESD diodes clamp the inputs when they try
to go more than one diode drop below V
SS
. They also
clamp any voltages that go well above V
DD
; their
breakdown voltage is high enough to allow normal
operation, but not low enough to protect against slow
over-voltage (beyond V
DD
) events. Very fast ESD
events (that meet the spec) are limited so that damage
does not occur.
In some applications, it may be necessary to prevent
excessive voltages from reaching the op amp inputs;
Figure 4-2 shows one approach to protecting these
inputs.
FIGURE 4-2: Protecting the Analog
Inputs.
A significant amount of current can flow out of the
inputs when the Common Mode voltage (V
CM
) is below
ground (V
SS
); See Figure 2-35.
4.1.3 INPUT CURRENT LIMITS
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the currents
into the input pins (see Section 1.1 “Absolute
Maximum Ratings †”).
Figure 4-3 shows one approach to protecting these
inputs. The resistors R
1
and R
2
limit the possible
currents in or out of the input pins (and the ESD diodes,
D
1
and D
2
). The diode currents will go through either
V
DD
or V
SS
.
FIGURE 4-3: Protecting the Analog
Inputs.
4.1.4 NORMAL OPERATION
The input stage of the MCP6401/1R/1U/2/4/6/7/9 op
amps use two differential input stages in parallel. One
operates at a low Common Mode input voltage (V
CM
),
while the other operates at a high V
CM
. With this
topology, the device operates with a V
CM
up to 300 mV
above V
DD
and 300 mV below V
SS
(see Figure 2-14).
The input offset voltage is measured at V
CM
= V
SS
–
0.3V and V
DD
+ 0.3V to ensure proper operation.
The transition between the input stages occurs when
V
CM
is near V
DD
– 1.1V (see Figures 2-6 and 2-7). For
the best distortion performance and gain linearity, with
non-inverting gains, avoid this region of operation.
Bond
Pad
Bond
Pad
Bond
Pad
V
DD
V
IN
+
V
SS
Input
Stage
Bond
Pad
V
IN
–
V
1
V
DD
D
1
V
2
D
2
MCP640x
V
OUT
U
1
V
1
R
1
V
DD
D
1
min(R
1
,R
2
)>
V
SS
–min(V
1
, V
2
)
2mA
V
2
R
2
D
2
MCP640x
V
OUT
U
1
min(R
1
,R
2
)>
max(V
1
,V
2
)–V
DD
2mA