Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsLinear ICsLinear IC - Op-amp Multi-purpose SOIC 8 N

 2009-2011 Microchip Technology Inc. DS22197B-page 1

MCP631/2/3/4/5/9

Features:

• Gain Bandwidth Product: 24 MHz (typical)

• Short Circuit Current: 70 mA (typical)

• Noise: 10 nV/Hz (typical, at 1 MHz)

• Rail-to-Rail Output

• Slew Rate: 10 V/µs (typical)

• Supply Current: 2.5 mA (typical)

• Power Supply: 2.5V to 5.5V

• Extended Temperature Range: -40°C to +125°C

Typical Applications:

• Driving A/D Converters

• Power Amplifier Control Loops

• Barcode Scanners

• Optical Detector Amplifier

Design Aids:

• SPICE Macro Models

•FilterLab

Software

• Microchip Advanced Part Selector (MAPS)

• Analog Demonstration and Evaluation Boards

• Application Notes

Description:

The Microchip Technology, Inc. MCP631/2/3/4/5/9 fam-

ily of operational amplifiers features high gain band-

width product (24 MHz, typical) and high output short

circuit current (70 mA, typical). Some also provide a

Chip Select pin (CS

) that supports a low-power mode

of operation. These amplifiers are optimized for high

speed, low noise and distortion, single-supply

operation with rail-to-rail output and an input that

includes the negative rail.

This family is offered in single (MCP631), single with

pin (MCP633), dual (MCP632), dual with two CS

pins (MCP635), quad (MCP634), and quad with two

Chip Select pins (MCP639). All devices are fully speci-

fied from -40°C to +125°C.

Typical Application Circuit

PowerDriverwithHighGain

OUT

MCP63X

24 MHz, 2.5 mA Op Amps

Summary of content (62 pages)

PAGE 1
MCP631/2/3/4/5/9 24 MHz, 2.5 mA Op Amps Features: Description: • • • • • • • • The Microchip Technology, Inc. MCP631/2/3/4/5/9 family of operational amplifiers features high gain bandwidth product (24 MHz, typical) and high output short circuit current (70 mA, typical). Some also provide a Chip Select pin (CS) that supports a low-power mode of operation.
PAGE 2
MCP631/2/3/4/5/9 Package Types MCP631 SOIC NC 1 8 NC NC 1 VIN– 2 7 VDD VIN– 2 VIN+ 3 6 VOUT VIN+ 3 VSS 4 5 NC MCP632 SOIC 6 VOUT 5 NC VINA– 2 7 VOUTB VINA– 2 6 VINB- VINA+ 3 5 VINB+ VSS 4 VOUTA 1 4 VIN- VIN+ 3 7 VOUTB 6 VINB– VOUT 1 6 VDD VSS 5 CS 2 VIN+ 3 5 VINB+ 12 VIND+ 11 VSS VINB+ 5 VINB- 6 10 VINC+ VOUTB 7 8 VOUTC MCP633 SOT-23-6 8 VDD EP 9 VINA- 2 VINA+ 3 VDD 4 2 MCP632 3x3 DFN * 8 VDD VSS 4 VSS 14 VOUTD 13 VIND- VOUTA 1 5 VDD VOUT 1 7 VDD VSS 4 VOUTA 1 VI
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MCP631/2/3/4/5/9 1.0 ELECTRICAL CHARACTERISTICS 1.1 Absolute Maximum Ratings † † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. VDD – VSS ..........................
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MCP631/2/3/4/5/9 TABLE 1-2: AC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT  VDD/2, VL = VDD/2, RL = 2 k to VL, CL = 50 pF and CS = VSS (refer to Figure 1-2). Parameters Sym Min Typ Max Units GBWP — 24 — MHz PM — 65 — ° ROUT — 20 —  THD+N — 0.
PAGE 5
MCP631/2/3/4/5/9 TABLE 1-4: TEMPERATURE SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VDD = +2.5V to +5.5V, VSS = GND. Parameters Sym Min Typ Max Units TA -40 — +125 °C Operating Temperature Range TA -40 — +125 °C Storage Temperature Range TA -65 — +150 °C Conditions Temperature Ranges Specified Temperature Range (Note 1) Thermal Package Resistances Thermal Resistance, 5L-SOT-23 θJA — 220.
PAGE 6
MCP631/2/3/4/5/9 CF 6.8 pF RG 10 k RF 10 k VREF = VDD/2 VP VDD VIN+ CB1 100 nF MCP63X CB2 2.2 µF VINVM RG 10 k RL 2 k RF 10 k CF 6.8 pF VOUT CL 50 pF VL FIGURE 1-2: AC and DC Test Circuit for Most Specifications. DS22197B-page 6  2009-2011 Microchip Technology Inc.
PAGE 7
MCP631/2/3/4/5/9 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
PAGE 8
MCP631/2/3/4/5/9 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 2 kto VL, CL = 50 pF and CS = VSS. 1.5 130 VDD = 2.5V Representative Part DC Open-Loop Gain (dB) Input Offset Voltage (mV) 2.0 +125°C +85°C +25°C -40°C 1.0 0.5 0.0 -0.5 -1.0 -1.5 VDD = 5.5V 120 115 VDD = 2.5V 110 105 100 3.0 2.5 2.0 1.5 1.0 0.5 -0.5 0.0 -2.0 125 -50 -25 Input Common Mode Voltage (V) 1.0 +125°C +85°C +25°C -40°C 0.5 0.0 -0.
PAGE 9
MCP631/2/3/4/5/9 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 2 kto VL, CL = 50 pF and CS = VSS. 2000 Input Bias, Offset Currents (pA) Input Current Magnitude (A) 1.E-03 1m 100µ 1.E-04 10µ 1.E-05 1µ 1.E-06 100n 1.E-07 10n 1.E-08 1n 1.E-09 100p 1.E-10 +125°C +85°C +25°C -40°C 10p 1.E-11 1p 1.E-12 IB 1500 1000 500 IOS 0 -500 -1000 Representative Part TA = +125°C VDD = 5.5V FIGURE 2-13: Input Bias Current vs.
PAGE 10
MCP631/2/3/4/5/9 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 2 kto VL, CL = 50 pF and CS = VSS. Other DC Voltages and Currents 3.5 3.0 VDD = 5.5V Supply Current (mA/amplifier) 100 VDD = 2.5V VOL – VSS 10 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 100 Power Supply Voltage (V) FIGURE 2-19: Supply Voltage. Supply Current vs. Power 3.5 RL = 2 kΩ 3.
PAGE 11
MCP631/2/3/4/5/9 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 2 kto VL, CL = 50 pF and CS = VSS. Frequency Response 34 80 70 60 50 CMRR PSRR+ PSRR- 30 20 55 24 50 22 45 GBWP 0 36 -30 34 100 -60 AOL -90 60 -120 40 -150 | AOL | -180 0 -210 -20 -240 65 60 55 50 22 GBWP 20 -50 -25 0 25 50 75 100 Ambient Temperature (°C) 45 40 125 FIGURE 2-23: Gain Bandwidth Product and Phase Margin vs.
PAGE 12
MCP631/2/3/4/5/9 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, 10 150 9 140 8 GN = 1 V/V GN = 2 V/V GN  4 V/V 7 6 5 4 3 2 100p 1n 1.0E-10 1.0E-09 Normalized Capacitive Load; CL/GN (F) FIGURE 2-27: Gain Peaking vs. Normalized Capacitive Load. DS22197B-page 12 RS = 0Ω RS = 100Ω RS = 1 kΩ 130 120 110 VCM = VDD/2 G = +1 V/V 100 90 80 70 60 1 0 10p 1.
PAGE 13
MCP631/2/3/4/5/9 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 2 kto VL, CL = 50 pF and CS = VSS. Noise and Distortion 1.E+4 10µ Input Noise; e ni(t) (µV) 20 1.E+3 1µ 1.E+2 100n 10n 1.E+1 1 1.E+0 10 1.E+1 10 5 0 -5 -10 Analog NPBW = 0.1 Hz Sample Rate = 2 SPS VOS = -3150 µV -15 100 1.E+2 1k 1.E+3 0 100k 10M 1M 1.E+7 1.E+5 1.E+6 10k 1.
PAGE 14
MCP631/2/3/4/5/9 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 2 kto VL, CL = 50 pF and CS = VSS. 2.5 Time Response 0.0 0.1 VOUT 0.2 Output Voltage (V) FIGURE 2-34: Step Response. 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 Output Voltage (V) VIN 0.3 0.4 0.5 Time (µs) 0.6 0.7 Non-inverting Small Signal VIN VOUT 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 Time (µs) FIGURE 2-37: Response.
PAGE 15
MCP631/2/3/4/5/9 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 2 kto VL, CL = 50 pF and CS = VSS. Maximum Output Voltage Swing (V P-P ) 10 VDD = 5.5V VDD = 2.5V 1 0.1 100k 1.E+05 1M 10M 1.E+06 1.E+07 Frequency (Hz) 100M 1.E+08 FIGURE 2-40: Maximum Output Voltage Swing vs. Frequency.  2009-2011 Microchip Technology Inc.
PAGE 16
MCP631/2/3/4/5/9 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 2 kto VL, CL = 50 pF and CS = VSS. Chip Select Response 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0.40 CS = VDD 0.35 CS Hysteresis (V) CS Current (µA) 2.6 0.30 0.25 0.15 0.05 0.00 FIGURE 2-41: Supply Voltage. CS Current vs. Power 3.0 -50 2.0 1.5 VOUT 1.0 On 0.5 0.0 Off 100 125 CS Hysteresis vs. Ambient 4 3 VDD = 2.5V 2 1 VDD = 5.
PAGE 17
MCP631/2/3/4/5/9 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, CS = VDD 1.E-06 1µ Output Leakage Current (A) 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8 -2.0 -2.2 CS = VDD = 5.5V 100n 1.E-07 10n 1.E-08 1n 1.E-09 +125°C +85°C Power Supply Voltage (V) FIGURE 2-47: Quiescent Current in Shutdown vs. Power Supply Voltage.  2009-2011 Microchip Technology Inc. 6.5 6.0 5.5 5.0 4.5 4.0 100p 1.E-10 3.5 3.0 2.5 2.0 1.5 1.0 0.
PAGE 18
MCP631/2/3/4/5/9 NOTES: DS22197B-page 18  2009-2011 Microchip Technology Inc.
PAGE 19
MCP631/2/3/4/5/9 3.0 PIN DESCRIPTIONS Descriptions of the pins are listed in Table 3-1.
PAGE 20
MCP631/2/3/4/5/9 3.4 Chip Select Digital Input (CS) This input (CS) is a CMOS, Schmitt-triggered input that places the part into a low-power mode of operation. 3.5 Exposed Thermal Pad (EP) There is an internal connection between the exposed thermal pad (EP) and the VSS pin; they must be connected to the same potential on the printed circuit board (PCB). This pad can be connected to a PCB ground plane to provide a larger heat sink. This improves the package thermal resistance (JA).
PAGE 21
MCP631/2/3/4/5/9 4.0 APPLICATIONS VDD The MCP631/2/3/4/5/9 family op amps is manufactured using the Microchip state-of-the-art CMOS process. It is designed for low cost, low power and high speed applications. Its low supply voltage, low quiescent current and wide bandwidth make the MCP631/2/3/4/5/ 9 ideal for battery-powered applications. 4.1 V1 V2 Input 4.1.1 The input devices are designed to not exhibit phase inversion when the input pins exceed the supply voltages.
PAGE 22
MCP631/2/3/4/5/9 4.2 Rail-to-Rail Output 4.2.1 VDD MAXIMUM OUTPUT VOLTAGE IDD The Maximum Output Voltage (see Figure 2-16 and Figure 2-17) describes the output range for a given load. For instance, the output voltage swings to within 50 mV of the negative rail with a 1 k load tied to VDD/ 2. 4.2.2 VOH Limited RL = 1 kΩ -ISC Limited RL = 100Ω RL = 10Ω 4.2.
PAGE 23
MCP631/2/3/4/5/9 The power de-rating across temperature for an op amp in a particular package can be easily calculated (assuming equal power dissipations): EQUATION 4-5: TJmax – TA n JA 1,000 Where: TJmax = absolute maximum junction temperature Several techniques are available to reduce TJA for a given POAmax: • Lower JA - Use another package - PCB layout (ground plane, etc.) - Heat sinks and air flow • Reduce POAmax - Increase RL - Limit IOUT (using RSER) - Decrease VDD 4.3 4.3.
PAGE 24
MCP631/2/3/4/5/9 CN and RN form a low-pass filter that affects the signal at VP. This filter has a single real pole at 1/(2RNCN). 1.E+05 100k CG = 10 pF CG = 32 pF CG = 100 pF CG = 320 pF CG = 1 nF Maximum Recommended R (Ω) F The largest value of RF that should be used depends on noise gain (see GN in Section 4.3.1 “Capacitive Loads”), CG and the open-loop gain’s phase shift. Figure 4-9 shows the maximum recommended RF for several CG values.
PAGE 25
MCP631/2/3/4/5/9 Keep sensitive traces short and straight. Separate them from interfering components and traces. This is especially important for high frequency (low rise time) signals. Sometimes, it helps to place guard traces next to victim traces. They should be on both sides of the victim trace, and as close as possible. Connect guard traces to ground plane at both ends, and in the middle for long traces. 4.7.3 H-BRIDGE DRIVER Figure 4-12 shows the MCP632 dual op amp used as a H-bridge driver.
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MCP631/2/3/4/5/9 5.0 DESIGN AIDS Microchip provides the basic design aids needed for the MCP631/2/3/4/5/9 family of op amps. 5.1 SPICE Macro Model The latest SPICE macro model for the MCP631/2/3/4/ 5/9 op amps is available on the Microchip web site at www.microchip.com. This model is intended to be an initial design tool that works well in the op amp’s linear region of operation over the temperature range. See the model file for information on its capabilities.
PAGE 27
MCP631/2/3/4/5/9 6.0 PACKAGING INFORMATION 6.1 Package Marking Information Example: 5-Lead SOT-23 (MCP631) XXNN YV25 Example: 6-Lead SOT-23 ( MCP633) XXNN JC25 8-Lead DFN (3x3)(MCP632) Example Device MCP632 DABM 1131 256 Code DABM Note: Applies to 8-Lead 3x3 DFN 8-Lead SOIC (150 mil) (MCP631, MCP632, MCP633) MCP631E SN e^^1131 3 256 NNN Legend: XX...
PAGE 28
MCP631/2/3/4/5/9 Package Marking Information (Continued) Example: 8-Lead TDFN (2 x 3) (MCP631) ABK 131 25 Example 10-Lead DFN (3x3) (MCP635) Device MCP635 BAFB 1131 256 Code BAFB Note: Applies to 10-Lead 3x3 DFN Example: 10-Lead MSOP (MCP635) 635EUN 131256 14-Lead SOIC (.150”) (MCP634) Example MCP634 3 E/SL e^^ 1131256 Legend: XX...
PAGE 29
MCP631/2/3/4/5/9 Package Marking Information (Continued) 14-Lead TSSOP (MCP634) Example XXXXXXXX YYWW NNN 634E/ST 1131 256 16-Lead QFN (4x4) (MCP639) PIN 1 PIN 1 Legend: XX...X Y YY WW NNN *e3 Note: Example 639 E/ML e^^3 131256 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free.
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MCP631/2/3/4/5/9 .
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MCP631/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009-2011 Microchip Technology Inc.
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MCP631/2/3/4/5/9 6-Lead Plastic Small Outline Transistor (CHY) [SOT-23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging b 4 N E E1 PIN 1 ID BY LASER MARK 1 2 3 e e1 D A A2 c φ L A1 L1 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 6 Pitch e 0.95 BSC Outside Lead Pitch e1 1.90 BSC Overall Height A 0.90 Molded Package Thickness A2 0.89 1.45 1.30 Standoff A1 0.
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MCP631/2/3/4/5/9 6-Lead Plastic Small Outline Transistor (CHY) [SOT-23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009-2011 Microchip Technology Inc.
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MCP631/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22197B-page 34  2009-2011 Microchip Technology Inc.
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MCP631/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009-2011 Microchip Technology Inc.
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MCP631/2/3/4/5/9 ! " # $ % & ' * *+,. / 0 !" . # # $ # / ## +22--- 2 DS22197B-page 36 ! - / 0 # 1 / % # # ! #  2009-2011 Microchip Technology Inc.
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MCP631/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009-2011 Microchip Technology Inc.
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MCP631/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22197B-page 38  2009-2011 Microchip Technology Inc.
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MCP631/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009-2011 Microchip Technology Inc.
PAGE 40
MCP631/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22197B-page 40  2009-2011 Microchip Technology Inc.
PAGE 41
MCP631/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009-2011 Microchip Technology Inc.
PAGE 42
MCP631/2/3/4/5/9 ' 1# ,4+ / 0 57 . # # $ # / ## +22--- 2 DS22197B-page 42 ! - / 0 # 1 / % # # ! #  2009-2011 Microchip Technology Inc.
PAGE 43
MCP631/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009-2011 Microchip Technology Inc.
PAGE 44
MCP631/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22197B-page 44  2009-2011 Microchip Technology Inc.
PAGE 45
MCP631/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009-2011 Microchip Technology Inc.
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MCP631/2/3/4/5/9 8+ & $ % 9 & .
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MCP631/2/3/4/5/9 10-Lead Plastic Micro Small Outline Package (UN) [MSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009-2011 Microchip Technology Inc.
PAGE 48
MCP631/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22197B-page 48  2009-2011 Microchip Technology Inc.
PAGE 49
MCP631/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009-2011 Microchip Technology Inc.
PAGE 50
MCP631/2/3/4/5/9 . # # $ # / ## +22--- 2 DS22197B-page 50 ! - / 0 # 1 / % # # ! #  2009-2011 Microchip Technology Inc.
PAGE 51
MCP631/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009-2011 Microchip Technology Inc.
PAGE 52
MCP631/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22197B-page 52  2009-2011 Microchip Technology Inc.
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MCP631/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009-2011 Microchip Technology Inc.
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MCP631/2/3/4/5/9 8; < " # $ % & ' =*=*+,4 / 0 <" .
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MCP631/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009-2011 Microchip Technology Inc.
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MCP631/2/3/4/5/9 NOTES: DS22197B-page 56  2009-2011 Microchip Technology Inc.
PAGE 57
MCP631/2/3/4/5/9 APPENDIX A: REVISION HISTORY Revision B (November 2011) The following is the list of modifications: 1. 2. 3. 4. 5. 6. Added the MCP634 and MCP639 amplifiers to the product family and the related information throughout the document. Added the 2x3 TDFN (8L), SOT23 (5L) package option for MCP631, SOT23 (6L) package option for MCP633, 4x4 QFN (16L) package option for MCP639, SOIC and TSSOP (14L) package options for MCP634 and the related information throughout the document.
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MCP631/2/3/4/5/9 NOTES: DS22197B-page 58  2009-2011 Microchip Technology Inc.
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MCP631/2/3/4/5/9 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO.
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MCP631/2/3/4/5/9 NOTES: DS22197B-page 60  2009-2011 Microchip Technology Inc.
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Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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