Datasheet

© 2009 Microchip Technology Inc. DS22196A-page 15
MCP6286
4.0 APPLICATION INFORMATION
The MCP6286 op amp is manufactured using
Microchip’s state-of-the-art CMOS process and is
specifically designed for low-power, low-noise
applications.
4.1 Input
4.1.1 PHASE REVERSAL
The MCP6286 op amp is designed to prevent phase
reversal when the input pins exceed the supply
voltages. Figure 2-31 shows the input voltage
exceeding the supply voltage without any phase
reversal.
4.1.2 INPUT VOLTAGE AND CURRENT
LIMITS
The ESD protection on the inputs can be depicted as
shown in Figure 4-1. This structure was chosen to
protect the input transistors and to minimize input bias
current (I
B
). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
V
SS
. They also clamp any voltage that goes too far
above V
DD
; their breakdown voltage is high enough to
allow normal operation and low enough to bypass ESD
events within the specified limits.
FIGURE 4-1: Simplified Analog Input ESD
Structures.
In order to prevent damage and/or improper operation
of these op amps, the circuit they are in must limit the
voltages and currents at the V
IN+
and V
IN-
pins (see
Absolute Maximum Ratings at the beginning of
Section 1.0 “Electrical Characteristics”). Figure 4-2
shows the recommended approach to protecting these
inputs. The internal ESD diodes prevent the input pins
(V
IN+
and V
IN-
) from going too far below ground, and
the resistors R
1
and R
2
limit the possible current drawn
out of the input pins. Diodes D
1
and D
2
prevent the
input pins (V
IN+
and V
IN-
) from going too far above V
DD
.
When implemented as shown, resistors R
1
and R
2
also
limit the current through D
1
and D
2
.
FIGURE 4-2: Protecting the Analog
Inputs.
It is also possible to connect the diodes to the left of the
resistors R
1
and R
2
. In this case, the currents through
the diodes D
1
and D
2
need to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC currents into the input pins (V
IN+
and
V
IN-
) should be very small. A significant amount of
current can flow out of the inputs when the common
mode voltage (V
CM
) is below ground (V
SS
). (See
Figure 2-33).
4.1.3 NORMAL OPERATION
The input stage of the MCP6286 op amp uses a PMOS
input stage. It operates at low common mode input
voltage (V
CM
), including ground. With this topology, the
device operates with a V
CM
up to V
DD
- 1.2V and 0.3V
below V
SS
. (See Figure 2-12).The input offset voltage
is measured at V
CM
= V
SS
– 0.3V and V
DD
- 1.2V to
ensure proper operation.
For a unity gain buffer, since V
OUT
is the same voltage
as the inverting input, V
OUT
must be maintained below
V
DD
–1.2V for correct operation.
4.2 Rail-to-Rail Output
The output voltage range of the MCP6286 op amp is
V
SS
+ 15 mV (minimum) and V
DD
– 15 mV (maximum)
when R
L
=10kΩ is connected to V
DD
/2 and
V
DD
= 5.5V. Refer to Figure 2-24 and Figure 2-25 for
more information.
Bond
Pad
Bond
Pad
Bond
Pad
V
DD
V
IN
+
V
SS
Input
Stage
Bond
Pad
V
IN
–
V
1
MCP6286
R
1
V
DD
D
1
R
1
>
V
SS
– (minimum expected V
1
)
2mA
R
2
>
V
SS
– (minimum expected V
2
)
2mA
V
2
R
2
D
2
R
3