Datasheet

MCP6281/1R/2/3/4/5
DS21811E-page 12 © 2008 Microchip Technology Inc.
4.0 APPLICATION INFORMATION
The MCP6281/1R/2/3/4/5 family of op amps is manu-
factured using Microchip's state-of-the-art CMOS
process. This family is specifically designed for low-
cost, low-power and general purpose applications.
The low supply voltage, low quiescent current and
wide bandwidth makes the MCP6281/1R/2/3/4/5 ideal
for battery-powered applications.
4.1 Rail-to-Rail Inputs
4.1.1 PHASE REVERSAL
The MCP6281/1R/2/3/4/5 op amp is designed to
prevent phase reversal when the input pins exceed the
supply voltages. Figure 2-32 shows the input voltage
exceeding the supply voltage without any phase
reversal.
4.1.2 INPUT VOLTAGE AND CURRENT
LIMITS
The ESD protection on the inputs can be depicted as
shown in Figure 4-1. This structure was chosen to
protect the input transistors, and to minimize input bias
current (I
B
). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
V
SS
. They also clamp any voltages that go too far
above V
DD
; their breakdown voltage is high enough to
allow normal operation, and low enough to bypass
quick ESD events within the specified limits.
FIGURE 4-1: Simplified Analog Input ESD
Structures.
In order to prevent damage and/or improper operation
of these op amps, the circuit they are in must limit the
currents and voltages at the V
IN
+ and V
IN
– pins (see
Absolute Maximum Ratings † at the beginning of
Section 1.0 “Electrical Characteristics”). Figure 4-2
shows the recommended approach to protecting these
inputs. The internal ESD diodes prevent the input pins
(V
IN
+ and V
IN
–) from going too far below ground, and
the resistors R
1
and R
2
limit the possible current drawn
out of the input pins. Diodes D
1
and D
2
prevent the
input pins (V
IN
+ and V
IN
–) from going too far above
V
DD
, and dump any currents onto V
DD
. When
implemented as shown, resistors R
1
and R
2
also limit
the current through D
1
and D
2
.
FIGURE 4-2: Protecting the Analog
Inputs.
It is also possible to connect the diodes to the left of
resistors R
1
and R
2
. In this case, current through the
diodes D
1
and D
2
needs to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (V
IN
+ and
V
IN
–) should be very small.
A significant amount of current can flow out of the
inputs when the common mode voltage (V
CM
) is below
ground (V
SS
); see Figure 2-31. Applications that are
high impedance may need to limit the usable voltage
range.
4.1.3 NORMAL OPERATION
The input stage of the MCP6281/1R/2/3/4/5 op amps
use two differential CMOS input stages in parallel. One
operates at low common mode input voltage (V
CM
),
while the other operates at high V
CM
. WIth this
topology, the device operates with V
CM
up to 0.3V
above V
DD
and 0.3V below V
SS
.
There is a transition in input behavior as V
CM
is
changed. It occurs when V
CM
is near V
DD
–1.2V (see
Figure 2-3 and Figure 2-6). For the best distortion
performance with non-inverting gains, avoid these
regions of operation.
Bond
Pad
Bond
Pad
Bond
Pad
V
DD
V
IN
+
V
SS
Input
Stage
Bond
Pad
V
IN
–
V
1
MCP628X
R
1
V
DD
D
1
R
1
>
V
SS
– (minimum expected V
1
)
2mA
R
2
>
V
SS
– (minimum expected V
2
)
2mA
V
2
R
2
D
2
R
3