Datasheet
Table Of Contents
- 1.0 Electrical Characteristics
- 2.0 Typical Performance Curves
- FIGURE 2-1: Input Offset Voltage.
- FIGURE 2-2: Input Bias Current at TA = +85˚C.
- FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage, with VDD = 2.0V.
- FIGURE 2-4: Input Offset Voltage Drift.
- FIGURE 2-5: Input Bias Current at TA = +125˚C.
- FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage, with VDD = 5.5V.
- FIGURE 2-7: Common Mode Input Voltage Range Lower Limit vs. Temperature.
- FIGURE 2-8: Input Offset Voltage vs. Output Voltage.
- FIGURE 2-9: CMRR, PSRR vs. Frequency.
- FIGURE 2-10: Common Mode Input Voltage Range Upper Limit vs. Temperature.
- FIGURE 2-11: Input Bias, Input Offset Currents vs. Temperature.
- FIGURE 2-12: CMRR, PSRR vs. Temperature.
- FIGURE 2-13: Input Bias, Offset Currents vs. Common Mode Input Voltage, with TA = +85˚C.
- FIGURE 2-14: Quiescent Current vs. Supply Voltage.
- FIGURE 2-15: Open-Loop Gain, Phase vs. Frequency.
- FIGURE 2-16: Input Bias, Offset Currents vs. Common Mode Input Voltage, with TA = +125˚C.
- FIGURE 2-17: Output Voltage Headroom vs. Output Current Magnitude.
- FIGURE 2-18: Gain Bandwidth Product, Phase Margin vs. Temperature.
- FIGURE 2-19: Maximum Output Voltage Swing vs. Frequency.
- FIGURE 2-20: Input Noise Voltage Density vs. Frequency.
- FIGURE 2-21: Output Short Circuit Current vs. Supply Voltage.
- FIGURE 2-22: Slew Rate vs. Temperature.
- FIGURE 2-23: Input Noise Voltage Density vs. Common Mode Input Voltage, with f = 1 kHz.
- FIGURE 2-24: Channel-to-Channel Separation vs. Frequency (MCP6272 and MCP6274).
- FIGURE 2-25: Quiescent Current vs. Chip Select (CS) Voltage, with VDD = 2.0V (MCP6273 and MCP6275 only).
- FIGURE 2-26: Large Signal Non-inverting Pulse Response.
- FIGURE 2-27: Small Signal Non-inverting Pulse Response.
- FIGURE 2-28: Quiescent Current vs. Chip Select (CS) Voltage, with VDD = 5.5V (MCP6273 and MCP6275 only).
- FIGURE 2-29: Large Signal Inverting Pulse Response.
- FIGURE 2-30: Small Signal Inverting Pulse Response.
- FIGURE 2-31: Chip Select (CS) to Amplifier Output Response Time, with VDD = 2.0V (MCP6273 and MCP6275 only).
- FIGURE 2-32: Input Current vs. Input Voltage.
- FIGURE 2-33: Chip Select (CS) to Amplifier Output Response Time, with VDD = 5,5V (MCP6273 and MCP6275 only).
- FIGURE 2-34: The MCP6271/1R/2/3/4/5 Show no Phase Reversal.
- 3.0 Pin Descriptions
- 4.0 Application Information
- 4.1 Rail-to-Rail Inputs
- 4.2 Rail-to-Rail Output
- 4.3 Capacitive Loads
- 4.4 MCP6273/5 Chip Select
- 4.5 Cascaded Dual Op Amps (MCP6275)
- 4.6 Unused Amplifiers
- 4.7 Supply Bypass
- 4.8 PCB Surface Leakage
- 4.9 Application Circuits
- FIGURE 4-8: Active Full-wave Rectifier.
- FIGURE 4-9: Non-Inverting Integrator.
- FIGURE 4-10: Isolating the Load with a Buffer.
- FIGURE 4-11: Cascaded Gain Circuit Configuration.
- FIGURE 4-12: Difference Amplifier Circuit.
- FIGURE 4-13: Integrator Circuit with Active Compensation.
- FIGURE 4-14: Second Order Multiple Feedback Low-Pass Filter with an Extra Pole- Zero Pair.
- FIGURE 4-15: Second Order Sallen-Key Low-Pass Filter with an Extra Pole-Zero Pair and Chip Select.
- FIGURE 4-16: Capacitorless Second Order Low-Pass Filter with Chip Select.
- 5.0 Design Tools
- 6.0 Packaging Information
© 2008 Microchip Technology Inc. DS21810F-page 7
MCP6271/1R/2/3/4/5
Note: Unless otherwise indicated, T
A
= +25°C, V
DD
= +2.0V to +5.5V, V
SS
=GND, V
CM
=V
DD
/2, V
OUT
≈ V
DD
/2,
V
L
= V
DD
/2, R
L
=10kΩ to V
L
, C
L
= 60 pF and CS is tied low.
FIGURE 2-7: Common Mode Input
Voltage Range Lower Limit vs. Temperature.
FIGURE 2-8: Input Offset Voltage vs.
Output Voltage.
FIGURE 2-9: CMRR, PSRR vs.
Frequency.
FIGURE 2-10: Common Mode Input
Voltage Range Upper Limit vs. Temperature.
FIGURE 2-11: Input Bias, Input Offset
Currents vs. Temperature.
FIGURE 2-12: CMRR, PSRR vs.
Temperature.
-0.50
-0.45
-0.40
-0.35
-0.30
-0.25
-0.20
-0.15
-0.10
-0.05
0.00
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Common Mode Input Voltage
Range Limit (V)
Typical lower (V
CM
– V
SS
) limit
V
DD
= 5.5V
V
DD
= 2.0V
-100
-50
0
50
100
150
200
250
300
0.00.51.01.52.02.53.03.54.04.55.05.5
Output Voltage (V)
Input Offset Voltage (µV)
V
DD
= 2.0V
V
CM
= V
SS
Representative Part
V
DD
= 5.5V
20
30
40
50
60
70
80
90
100
110
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06
Frequency (Hz)
CMRR, PSRR (dB)
1 10k 100k 1M10010 1k
PSRR–
PSRR+
CMRR
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
-50-250 255075100125
Ambient Temperature (°C)
Common Mode Input Voltage
Range Limit (V)
Typical upper (V
CM
– V
DD
) limit
V
DD
= 5.5
V
V
DD
= 2.0V
1
10
100
1,000
10,000
45 55 65 75 85 95 105 115 125
Ambient Temperature (°C)
Input Bias, Offset Currents
(pA)
Input Bias Current
V
CM
= V
DD
V
DD
= 5.5V
Input Offset Current
60
70
80
90
100
110
120
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
PSRR, CMRR (dB)
PSRR
(V
CM
= V
SS
)
CMRR