Datasheet
Table Of Contents
- 1.0 Electrical Characteristics
- 2.0 Typical Performance Curves
- FIGURE 2-1: Input Offset Voltage.
- FIGURE 2-2: Input Bias Current at TA = +85˚C.
- FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage, with VDD = 2.0V.
- FIGURE 2-4: Input Offset Voltage Drift.
- FIGURE 2-5: Input Bias Current at TA = +125˚C.
- FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage, with VDD = 5.5V.
- FIGURE 2-7: Common Mode Input Voltage Range Lower Limit vs. Temperature.
- FIGURE 2-8: Input Offset Voltage vs. Output Voltage.
- FIGURE 2-9: CMRR, PSRR vs. Frequency.
- FIGURE 2-10: Common Mode Input Voltage Range Upper Limit vs. Temperature.
- FIGURE 2-11: Input Bias, Input Offset Currents vs. Temperature.
- FIGURE 2-12: CMRR, PSRR vs. Temperature.
- FIGURE 2-13: Input Bias, Offset Currents vs. Common Mode Input Voltage, with TA = +85˚C.
- FIGURE 2-14: Quiescent Current vs. Supply Voltage.
- FIGURE 2-15: Open-Loop Gain, Phase vs. Frequency.
- FIGURE 2-16: Input Bias, Offset Currents vs. Common Mode Input Voltage, with TA = +125˚C.
- FIGURE 2-17: Output Voltage Headroom vs. Output Current Magnitude.
- FIGURE 2-18: Gain Bandwidth Product, Phase Margin vs. Temperature.
- FIGURE 2-19: Maximum Output Voltage Swing vs. Frequency.
- FIGURE 2-20: Input Noise Voltage Density vs. Frequency.
- FIGURE 2-21: Output Short Circuit Current vs. Supply Voltage.
- FIGURE 2-22: Slew Rate vs. Temperature.
- FIGURE 2-23: Input Noise Voltage Density vs. Common Mode Input Voltage, with f = 1 kHz.
- FIGURE 2-24: Channel-to-Channel Separation vs. Frequency (MCP6272 and MCP6274).
- FIGURE 2-25: Quiescent Current vs. Chip Select (CS) Voltage, with VDD = 2.0V (MCP6273 and MCP6275 only).
- FIGURE 2-26: Large Signal Non-inverting Pulse Response.
- FIGURE 2-27: Small Signal Non-inverting Pulse Response.
- FIGURE 2-28: Quiescent Current vs. Chip Select (CS) Voltage, with VDD = 5.5V (MCP6273 and MCP6275 only).
- FIGURE 2-29: Large Signal Inverting Pulse Response.
- FIGURE 2-30: Small Signal Inverting Pulse Response.
- FIGURE 2-31: Chip Select (CS) to Amplifier Output Response Time, with VDD = 2.0V (MCP6273 and MCP6275 only).
- FIGURE 2-32: Input Current vs. Input Voltage.
- FIGURE 2-33: Chip Select (CS) to Amplifier Output Response Time, with VDD = 5,5V (MCP6273 and MCP6275 only).
- FIGURE 2-34: The MCP6271/1R/2/3/4/5 Show no Phase Reversal.
- 3.0 Pin Descriptions
- 4.0 Application Information
- 4.1 Rail-to-Rail Inputs
- 4.2 Rail-to-Rail Output
- 4.3 Capacitive Loads
- 4.4 MCP6273/5 Chip Select
- 4.5 Cascaded Dual Op Amps (MCP6275)
- 4.6 Unused Amplifiers
- 4.7 Supply Bypass
- 4.8 PCB Surface Leakage
- 4.9 Application Circuits
- FIGURE 4-8: Active Full-wave Rectifier.
- FIGURE 4-9: Non-Inverting Integrator.
- FIGURE 4-10: Isolating the Load with a Buffer.
- FIGURE 4-11: Cascaded Gain Circuit Configuration.
- FIGURE 4-12: Difference Amplifier Circuit.
- FIGURE 4-13: Integrator Circuit with Active Compensation.
- FIGURE 4-14: Second Order Multiple Feedback Low-Pass Filter with an Extra Pole- Zero Pair.
- FIGURE 4-15: Second Order Sallen-Key Low-Pass Filter with an Extra Pole-Zero Pair and Chip Select.
- FIGURE 4-16: Capacitorless Second Order Low-Pass Filter with Chip Select.
- 5.0 Design Tools
- 6.0 Packaging Information
MCP6271/1R/2/3/4/5
DS21810F-page 6 © 2008 Microchip Technology Inc.
2.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, T
A
= +25°C, V
DD
= +2.0V to +5.5V, V
SS
=GND, V
CM
=V
DD
/2, V
OUT
≈ V
DD
/2,
V
L
= V
DD
/2, R
L
=10kΩ to V
L
, C
L
= 60 pF and CS is tied low.
FIGURE 2-1: Input Offset Voltage.
FIGURE 2-2: Input Bias Current at
T
A
=+85°C.
FIGURE 2-3: Input Offset Voltage vs.
Common Mode Input Voltage, with V
DD
=2.0V.
FIGURE 2-4: Input Offset Voltage Drift.
FIGURE 2-5: Input Bias Current at
T
A
= +125°C.
FIGURE 2-6: Input Offset Voltage vs.
Common Mode Input Voltage, with V
DD
=5.5V.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
0%
2%
4%
6%
8%
10%
12%
14%
16%
18%
-3.0
-2.4
-1.8
-1.2
-0.6
0.0
0.6
1.2
1.8
2.4
3.0
Input Offset Voltage (mV)
Percentage of Occurrences
832 Samples
V
CM
= V
SS
0%
4%
8%
12%
16%
20%
24%
28%
32%
0 102030405060708090100
Input Bias Current (pA)
Percentage of Occurrences
422 Samples
T
A
= 85°C
-100
-50
0
50
100
150
200
250
300
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
Common Mode Input Voltage (V)
Input Offset Voltage (µV)
V
DD
= 2.0V
T
A
= +125°C
T
A
= +85°C
T
A
= +25°C
T
A
= -40°C
0%
2%
4%
6%
8%
10%
12%
14%
-10
-8
-6
-4
-2
0
2
4
6
8
10
Input Offset Voltage Drift (µV/°C)
Percentage of Occurrences
832 Samples
V
CM
= V
SS
T
A
= -40°C to +125°C
0%
2%
4%
6%
8%
10%
12%
14%
16%
18%
20%
22%
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
Input Bias Current (nA)
Percentage of Occurrences
422 Samples
T
A
= +125°C
-100
-50
0
50
100
150
200
250
300
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Common Mode Input Voltage (V)
Input Offset Voltage (µV)
V
DD
= 5.5V
T
A
= +85°C
T
A
= +25°C
T
A
= -40°C
T
A
= +125°C