Datasheet
Table Of Contents
- 1.0 Electrical Characteristics
- 2.0 Typical Performance Curves
- FIGURE 2-1: Input Offset Voltage.
- FIGURE 2-2: Input Bias Current at TA = +85˚C.
- FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage, with VDD = 2.0V.
- FIGURE 2-4: Input Offset Voltage Drift.
- FIGURE 2-5: Input Bias Current at TA = +125˚C.
- FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage, with VDD = 5.5V.
- FIGURE 2-7: Common Mode Input Voltage Range Lower Limit vs. Temperature.
- FIGURE 2-8: Input Offset Voltage vs. Output Voltage.
- FIGURE 2-9: CMRR, PSRR vs. Frequency.
- FIGURE 2-10: Common Mode Input Voltage Range Upper Limit vs. Temperature.
- FIGURE 2-11: Input Bias, Input Offset Currents vs. Temperature.
- FIGURE 2-12: CMRR, PSRR vs. Temperature.
- FIGURE 2-13: Input Bias, Offset Currents vs. Common Mode Input Voltage, with TA = +85˚C.
- FIGURE 2-14: Quiescent Current vs. Supply Voltage.
- FIGURE 2-15: Open-Loop Gain, Phase vs. Frequency.
- FIGURE 2-16: Input Bias, Offset Currents vs. Common Mode Input Voltage, with TA = +125˚C.
- FIGURE 2-17: Output Voltage Headroom vs. Output Current Magnitude.
- FIGURE 2-18: Gain Bandwidth Product, Phase Margin vs. Temperature.
- FIGURE 2-19: Maximum Output Voltage Swing vs. Frequency.
- FIGURE 2-20: Input Noise Voltage Density vs. Frequency.
- FIGURE 2-21: Output Short Circuit Current vs. Supply Voltage.
- FIGURE 2-22: Slew Rate vs. Temperature.
- FIGURE 2-23: Input Noise Voltage Density vs. Common Mode Input Voltage, with f = 1 kHz.
- FIGURE 2-24: Channel-to-Channel Separation vs. Frequency (MCP6272 and MCP6274).
- FIGURE 2-25: Quiescent Current vs. Chip Select (CS) Voltage, with VDD = 2.0V (MCP6273 and MCP6275 only).
- FIGURE 2-26: Large Signal Non-inverting Pulse Response.
- FIGURE 2-27: Small Signal Non-inverting Pulse Response.
- FIGURE 2-28: Quiescent Current vs. Chip Select (CS) Voltage, with VDD = 5.5V (MCP6273 and MCP6275 only).
- FIGURE 2-29: Large Signal Inverting Pulse Response.
- FIGURE 2-30: Small Signal Inverting Pulse Response.
- FIGURE 2-31: Chip Select (CS) to Amplifier Output Response Time, with VDD = 2.0V (MCP6273 and MCP6275 only).
- FIGURE 2-32: Input Current vs. Input Voltage.
- FIGURE 2-33: Chip Select (CS) to Amplifier Output Response Time, with VDD = 5,5V (MCP6273 and MCP6275 only).
- FIGURE 2-34: The MCP6271/1R/2/3/4/5 Show no Phase Reversal.
- 3.0 Pin Descriptions
- 4.0 Application Information
- 4.1 Rail-to-Rail Inputs
- 4.2 Rail-to-Rail Output
- 4.3 Capacitive Loads
- 4.4 MCP6273/5 Chip Select
- 4.5 Cascaded Dual Op Amps (MCP6275)
- 4.6 Unused Amplifiers
- 4.7 Supply Bypass
- 4.8 PCB Surface Leakage
- 4.9 Application Circuits
- FIGURE 4-8: Active Full-wave Rectifier.
- FIGURE 4-9: Non-Inverting Integrator.
- FIGURE 4-10: Isolating the Load with a Buffer.
- FIGURE 4-11: Cascaded Gain Circuit Configuration.
- FIGURE 4-12: Difference Amplifier Circuit.
- FIGURE 4-13: Integrator Circuit with Active Compensation.
- FIGURE 4-14: Second Order Multiple Feedback Low-Pass Filter with an Extra Pole- Zero Pair.
- FIGURE 4-15: Second Order Sallen-Key Low-Pass Filter with an Extra Pole-Zero Pair and Chip Select.
- FIGURE 4-16: Capacitorless Second Order Low-Pass Filter with Chip Select.
- 5.0 Design Tools
- 6.0 Packaging Information
© 2008 Microchip Technology Inc. DS21810F-page 5
MCP6271/1R/2/3/4/5
1.1 Test Circuits
The test circuits used for the DC and AC tests are
shown in Figure 1-2 and Figure 1-3. The bypass
capacitors are laid out according to the rules discussed
in Section 4.7 “Supply Bypass”.
FIGURE 1-2: AC and DC Test Circuit for
Most Non-Inverting Gain Conditions.
FIGURE 1-3: AC and DC Test Circuit for
Most Inverting Gain Conditions.
V
DD
MCP627X
R
G
R
F
R
N
V
OUT
V
IN
V
DD
/2
1µF
C
L
R
L
V
L
0.1 µF
V
DD
MCP627X
R
G
R
F
R
N
V
OUT
V
DD
/2
V
IN
1µF
C
L
R
L
V
L
0.1 µF