Datasheet
Table Of Contents
- 1.0 Electrical Characteristics
- 2.0 Typical Performance Curves
- FIGURE 2-1: Input Offset Voltage.
- FIGURE 2-2: Input Bias Current at TA = +85˚C.
- FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage, with VDD = 2.0V.
- FIGURE 2-4: Input Offset Voltage Drift.
- FIGURE 2-5: Input Bias Current at TA = +125˚C.
- FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage, with VDD = 5.5V.
- FIGURE 2-7: Common Mode Input Voltage Range Lower Limit vs. Temperature.
- FIGURE 2-8: Input Offset Voltage vs. Output Voltage.
- FIGURE 2-9: CMRR, PSRR vs. Frequency.
- FIGURE 2-10: Common Mode Input Voltage Range Upper Limit vs. Temperature.
- FIGURE 2-11: Input Bias, Input Offset Currents vs. Temperature.
- FIGURE 2-12: CMRR, PSRR vs. Temperature.
- FIGURE 2-13: Input Bias, Offset Currents vs. Common Mode Input Voltage, with TA = +85˚C.
- FIGURE 2-14: Quiescent Current vs. Supply Voltage.
- FIGURE 2-15: Open-Loop Gain, Phase vs. Frequency.
- FIGURE 2-16: Input Bias, Offset Currents vs. Common Mode Input Voltage, with TA = +125˚C.
- FIGURE 2-17: Output Voltage Headroom vs. Output Current Magnitude.
- FIGURE 2-18: Gain Bandwidth Product, Phase Margin vs. Temperature.
- FIGURE 2-19: Maximum Output Voltage Swing vs. Frequency.
- FIGURE 2-20: Input Noise Voltage Density vs. Frequency.
- FIGURE 2-21: Output Short Circuit Current vs. Supply Voltage.
- FIGURE 2-22: Slew Rate vs. Temperature.
- FIGURE 2-23: Input Noise Voltage Density vs. Common Mode Input Voltage, with f = 1 kHz.
- FIGURE 2-24: Channel-to-Channel Separation vs. Frequency (MCP6272 and MCP6274).
- FIGURE 2-25: Quiescent Current vs. Chip Select (CS) Voltage, with VDD = 2.0V (MCP6273 and MCP6275 only).
- FIGURE 2-26: Large Signal Non-inverting Pulse Response.
- FIGURE 2-27: Small Signal Non-inverting Pulse Response.
- FIGURE 2-28: Quiescent Current vs. Chip Select (CS) Voltage, with VDD = 5.5V (MCP6273 and MCP6275 only).
- FIGURE 2-29: Large Signal Inverting Pulse Response.
- FIGURE 2-30: Small Signal Inverting Pulse Response.
- FIGURE 2-31: Chip Select (CS) to Amplifier Output Response Time, with VDD = 2.0V (MCP6273 and MCP6275 only).
- FIGURE 2-32: Input Current vs. Input Voltage.
- FIGURE 2-33: Chip Select (CS) to Amplifier Output Response Time, with VDD = 5,5V (MCP6273 and MCP6275 only).
- FIGURE 2-34: The MCP6271/1R/2/3/4/5 Show no Phase Reversal.
- 3.0 Pin Descriptions
- 4.0 Application Information
- 4.1 Rail-to-Rail Inputs
- 4.2 Rail-to-Rail Output
- 4.3 Capacitive Loads
- 4.4 MCP6273/5 Chip Select
- 4.5 Cascaded Dual Op Amps (MCP6275)
- 4.6 Unused Amplifiers
- 4.7 Supply Bypass
- 4.8 PCB Surface Leakage
- 4.9 Application Circuits
- FIGURE 4-8: Active Full-wave Rectifier.
- FIGURE 4-9: Non-Inverting Integrator.
- FIGURE 4-10: Isolating the Load with a Buffer.
- FIGURE 4-11: Cascaded Gain Circuit Configuration.
- FIGURE 4-12: Difference Amplifier Circuit.
- FIGURE 4-13: Integrator Circuit with Active Compensation.
- FIGURE 4-14: Second Order Multiple Feedback Low-Pass Filter with an Extra Pole- Zero Pair.
- FIGURE 4-15: Second Order Sallen-Key Low-Pass Filter with an Extra Pole-Zero Pair and Chip Select.
- FIGURE 4-16: Capacitorless Second Order Low-Pass Filter with Chip Select.
- 5.0 Design Tools
- 6.0 Packaging Information
MCP6271/1R/2/3/4/5
DS21810F-page 4 © 2008 Microchip Technology Inc.
TEMPERATURE SPECIFICATIONS
MCP6273/MCP6275 CHIP SELECT SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, V
DD
= +2.0V to +5.5V and V
SS
=GND.
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Specified Temperature Range T
A
–40 — +125 °C
Operating Temperature Range T
A
–40 — +125 °C Note
Storage Temperature Range T
A
–65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 5L-SOT-23 θ
JA
—256—°C/W
Thermal Resistance, 6L-SOT-23 θ
JA
—230—°C/W
Thermal Resistance, 8L-PDIP θ
JA
—85—°C/W
Thermal Resistance, 8L-SOIC θ
JA
—163—°C/W
Thermal Resistance, 8L-MSOP θ
JA
—206—°C/W
Thermal Resistance, 14L-PDIP
θ
JA
—
70
—
°C/W
Thermal Resistance, 14L-SOIC
θ
JA
—
120
—
°C/W
Thermal Resistance, 14L-TSSOP
θ
JA
—
100
—
°C/W
Note: The Junction Temperature (T
J
) must not exceed the Absolute Maximum specification of +150°C.
Electrical Characteristics: Unless otherwise indicated, T
A
= +25°C, V
DD
= +2.0V to +5.5V, V
SS
=GND,
V
CM
=V
DD
/2, V
OUT
≈ V
DD
/2, V
L
= V
DD
/2, R
L
=10kΩ to V
DD
/2, C
L
= 60 pF and CS is tied low.
Parameters Sym Min Typ Max Units Conditions
CS
Low Specifications
CS
Logic Threshold, Low V
IL
V
SS
—0.2V
DD
V
CS
Input Current, Low I
CSL
—0.01— µACS = V
SS
CS High Specifications
CS
Logic Threshold, High V
IH
0.8V
DD
—V
DD
V
CS
Input Current, High I
CSH
—0.7 2 µACS = V
DD
GND Current per Amplifier I
SS
— –0.7 — µA CS = V
DD
Amplifier Output Leakage — — 0.01 — µA CS = V
DD
Dynamic Specifications (Note 1)
CS
Low to Valid Amplifier
Output, Turn on Time
t
ON
—410µsCS Low ≤ 0.2 V
DD
, G = +1 V/V,
V
IN
= V
DD
/2, V
OUT
= 0.9 V
DD
/2,
V
DD
= 5.0V
CS
High to Amplifier Output
High-Z
t
OFF
—0.01— µsCS High ≥ 0.8 V
DD
, G = +1 V/V,
V
IN
= V
DD
/2, V
OUT
= 0.1 V
DD
/2
Hysteresis V
HYST
—0.6— VV
DD
= 5V
Note 1: The input condition (V
IN
) specified applies to both op amp A and B of the MCP6275. The dynamic
specification is tested at the output of op amp B (V
OUTB
).