Datasheet
Table Of Contents
- 1.0 Electrical Characteristics
- 2.0 Typical Performance Curves
- FIGURE 2-1: Input Offset Voltage.
- FIGURE 2-2: Input Bias Current at TA = +85˚C.
- FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage, with VDD = 2.0V.
- FIGURE 2-4: Input Offset Voltage Drift.
- FIGURE 2-5: Input Bias Current at TA = +125˚C.
- FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage, with VDD = 5.5V.
- FIGURE 2-7: Common Mode Input Voltage Range Lower Limit vs. Temperature.
- FIGURE 2-8: Input Offset Voltage vs. Output Voltage.
- FIGURE 2-9: CMRR, PSRR vs. Frequency.
- FIGURE 2-10: Common Mode Input Voltage Range Upper Limit vs. Temperature.
- FIGURE 2-11: Input Bias, Input Offset Currents vs. Temperature.
- FIGURE 2-12: CMRR, PSRR vs. Temperature.
- FIGURE 2-13: Input Bias, Offset Currents vs. Common Mode Input Voltage, with TA = +85˚C.
- FIGURE 2-14: Quiescent Current vs. Supply Voltage.
- FIGURE 2-15: Open-Loop Gain, Phase vs. Frequency.
- FIGURE 2-16: Input Bias, Offset Currents vs. Common Mode Input Voltage, with TA = +125˚C.
- FIGURE 2-17: Output Voltage Headroom vs. Output Current Magnitude.
- FIGURE 2-18: Gain Bandwidth Product, Phase Margin vs. Temperature.
- FIGURE 2-19: Maximum Output Voltage Swing vs. Frequency.
- FIGURE 2-20: Input Noise Voltage Density vs. Frequency.
- FIGURE 2-21: Output Short Circuit Current vs. Supply Voltage.
- FIGURE 2-22: Slew Rate vs. Temperature.
- FIGURE 2-23: Input Noise Voltage Density vs. Common Mode Input Voltage, with f = 1 kHz.
- FIGURE 2-24: Channel-to-Channel Separation vs. Frequency (MCP6272 and MCP6274).
- FIGURE 2-25: Quiescent Current vs. Chip Select (CS) Voltage, with VDD = 2.0V (MCP6273 and MCP6275 only).
- FIGURE 2-26: Large Signal Non-inverting Pulse Response.
- FIGURE 2-27: Small Signal Non-inverting Pulse Response.
- FIGURE 2-28: Quiescent Current vs. Chip Select (CS) Voltage, with VDD = 5.5V (MCP6273 and MCP6275 only).
- FIGURE 2-29: Large Signal Inverting Pulse Response.
- FIGURE 2-30: Small Signal Inverting Pulse Response.
- FIGURE 2-31: Chip Select (CS) to Amplifier Output Response Time, with VDD = 2.0V (MCP6273 and MCP6275 only).
- FIGURE 2-32: Input Current vs. Input Voltage.
- FIGURE 2-33: Chip Select (CS) to Amplifier Output Response Time, with VDD = 5,5V (MCP6273 and MCP6275 only).
- FIGURE 2-34: The MCP6271/1R/2/3/4/5 Show no Phase Reversal.
- 3.0 Pin Descriptions
- 4.0 Application Information
- 4.1 Rail-to-Rail Inputs
- 4.2 Rail-to-Rail Output
- 4.3 Capacitive Loads
- 4.4 MCP6273/5 Chip Select
- 4.5 Cascaded Dual Op Amps (MCP6275)
- 4.6 Unused Amplifiers
- 4.7 Supply Bypass
- 4.8 PCB Surface Leakage
- 4.9 Application Circuits
- FIGURE 4-8: Active Full-wave Rectifier.
- FIGURE 4-9: Non-Inverting Integrator.
- FIGURE 4-10: Isolating the Load with a Buffer.
- FIGURE 4-11: Cascaded Gain Circuit Configuration.
- FIGURE 4-12: Difference Amplifier Circuit.
- FIGURE 4-13: Integrator Circuit with Active Compensation.
- FIGURE 4-14: Second Order Multiple Feedback Low-Pass Filter with an Extra Pole- Zero Pair.
- FIGURE 4-15: Second Order Sallen-Key Low-Pass Filter with an Extra Pole-Zero Pair and Chip Select.
- FIGURE 4-16: Capacitorless Second Order Low-Pass Filter with Chip Select.
- 5.0 Design Tools
- 6.0 Packaging Information
© 2008 Microchip Technology Inc. DS21810F-page 3
MCP6271/1R/2/3/4/5
AC ELECTRICAL SPECIFICATIONS
FIGURE 1-1: Timing Diagram for the Chip
Select (CS
) pin on the MCP6273 and MCP6275.
Output
Maximum Output Voltage Swing V
OL
, V
OH
V
SS
+15 — V
DD
− 15 mV 0.5V input overdrive (Note 4)
Output Short Circuit Current I
SC
—±25—mA
Power Supply
Supply Voltage V
DD
2.0 — 6.0 V
Quiescent Current per Amplifier I
Q
100 170 240 µA I
O
= 0
Electrical Characteristics: Unless otherwise indicated, T
A
= +25°C, V
DD
= +2.0V to +5.5V, V
SS
= GND, V
CM
=V
DD
/2,
V
OUT
≈ V
DD
/2, V
L
= V
DD
/2, R
L
=10kΩ to V
L
, C
L
= 60 pF and CS is tied low. (Refer to Figure 1-2 and Figure 1-3).
Parameters Sym Min Typ Max Units Conditions
AC Response
Gain Bandwidth Product GBWP — 2.0 — MHz
Phase Margin PM — 65 — ° G = +1 V/V
Slew Rate SR — 0.9 — V/µs
Noise
Input Noise Voltage E
ni
— 4.6 — µV
P-P
f = 0.1 Hz to 10 Hz
Input Noise Voltage Density e
ni
— 20 — nV/√Hz f = 1 kHz
Input Noise Current Density i
ni
— 3—fA/√Hz f = 1 kHz
DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, T
A
= +25°C, V
DD
= +2.0V to +5.5V, V
SS
= GND, V
CM
=V
DD
/2,
V
OUT
≈ V
DD
/2, V
L
= V
DD
/2, R
L
=10kΩ to V
L
and CS is tied low. (Refer to Figure 1-2 and Figure 1-3).
Parameters Sym Min Typ Max Units Conditions
Note 1: The MCP6275’s V
CM
for op amp B (pins V
OUTA
/V
INB
+ and V
INB
–) is V
SS
+100mV.
2: The current at the MCP6275’s V
INB
– pin is specified by I
B
only.
3: This specification does not apply to the MCP6275’s V
OUTA
/V
INB
+ pin.
4: The MCP6275’s V
INB
– pin (op amp B) has a common mode input voltage range (V
CMR
) of V
SS
+ 100 mV to
V
DD
– 100 mV. CMRR is not measured for op amp B of the MCP6275. The MCP6275’s V
OUTA
/V
INB
+ pin (op amp B)
has a voltage range specified by V
OH
and V
OL
.
5: Set by design and characterization.
6: Does not apply to op amp B of the MCP6275.
7: All parts with date codes November 2007 and later have been screened to ensure operation at V
DD
= 6.0V. However,
the other minimum and maximum specifications are measured at 2.0V and 5.5V.
V
IL
High-Z
t
ON
V
IH
CS
t
OFF
V
OUT
-0.7 µA
High-Z
I
SS
I
CS
0.7 µA
0.7 µA
-0.7 µA
-170 µA
10 nA
(typical)
(typical)
(typical)
(typical)
(typical)
(typical)