Datasheet
Table Of Contents
- 1.0 Electrical Characteristics
- 2.0 Typical Performance Curves
- FIGURE 2-1: Input Offset Voltage.
- FIGURE 2-2: Input Bias Current at TA = +85˚C.
- FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage, with VDD = 2.0V.
- FIGURE 2-4: Input Offset Voltage Drift.
- FIGURE 2-5: Input Bias Current at TA = +125˚C.
- FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage, with VDD = 5.5V.
- FIGURE 2-7: Common Mode Input Voltage Range Lower Limit vs. Temperature.
- FIGURE 2-8: Input Offset Voltage vs. Output Voltage.
- FIGURE 2-9: CMRR, PSRR vs. Frequency.
- FIGURE 2-10: Common Mode Input Voltage Range Upper Limit vs. Temperature.
- FIGURE 2-11: Input Bias, Input Offset Currents vs. Temperature.
- FIGURE 2-12: CMRR, PSRR vs. Temperature.
- FIGURE 2-13: Input Bias, Offset Currents vs. Common Mode Input Voltage, with TA = +85˚C.
- FIGURE 2-14: Quiescent Current vs. Supply Voltage.
- FIGURE 2-15: Open-Loop Gain, Phase vs. Frequency.
- FIGURE 2-16: Input Bias, Offset Currents vs. Common Mode Input Voltage, with TA = +125˚C.
- FIGURE 2-17: Output Voltage Headroom vs. Output Current Magnitude.
- FIGURE 2-18: Gain Bandwidth Product, Phase Margin vs. Temperature.
- FIGURE 2-19: Maximum Output Voltage Swing vs. Frequency.
- FIGURE 2-20: Input Noise Voltage Density vs. Frequency.
- FIGURE 2-21: Output Short Circuit Current vs. Supply Voltage.
- FIGURE 2-22: Slew Rate vs. Temperature.
- FIGURE 2-23: Input Noise Voltage Density vs. Common Mode Input Voltage, with f = 1 kHz.
- FIGURE 2-24: Channel-to-Channel Separation vs. Frequency (MCP6272 and MCP6274).
- FIGURE 2-25: Quiescent Current vs. Chip Select (CS) Voltage, with VDD = 2.0V (MCP6273 and MCP6275 only).
- FIGURE 2-26: Large Signal Non-inverting Pulse Response.
- FIGURE 2-27: Small Signal Non-inverting Pulse Response.
- FIGURE 2-28: Quiescent Current vs. Chip Select (CS) Voltage, with VDD = 5.5V (MCP6273 and MCP6275 only).
- FIGURE 2-29: Large Signal Inverting Pulse Response.
- FIGURE 2-30: Small Signal Inverting Pulse Response.
- FIGURE 2-31: Chip Select (CS) to Amplifier Output Response Time, with VDD = 2.0V (MCP6273 and MCP6275 only).
- FIGURE 2-32: Input Current vs. Input Voltage.
- FIGURE 2-33: Chip Select (CS) to Amplifier Output Response Time, with VDD = 5,5V (MCP6273 and MCP6275 only).
- FIGURE 2-34: The MCP6271/1R/2/3/4/5 Show no Phase Reversal.
- 3.0 Pin Descriptions
- 4.0 Application Information
- 4.1 Rail-to-Rail Inputs
- 4.2 Rail-to-Rail Output
- 4.3 Capacitive Loads
- 4.4 MCP6273/5 Chip Select
- 4.5 Cascaded Dual Op Amps (MCP6275)
- 4.6 Unused Amplifiers
- 4.7 Supply Bypass
- 4.8 PCB Surface Leakage
- 4.9 Application Circuits
- FIGURE 4-8: Active Full-wave Rectifier.
- FIGURE 4-9: Non-Inverting Integrator.
- FIGURE 4-10: Isolating the Load with a Buffer.
- FIGURE 4-11: Cascaded Gain Circuit Configuration.
- FIGURE 4-12: Difference Amplifier Circuit.
- FIGURE 4-13: Integrator Circuit with Active Compensation.
- FIGURE 4-14: Second Order Multiple Feedback Low-Pass Filter with an Extra Pole- Zero Pair.
- FIGURE 4-15: Second Order Sallen-Key Low-Pass Filter with an Extra Pole-Zero Pair and Chip Select.
- FIGURE 4-16: Capacitorless Second Order Low-Pass Filter with Chip Select.
- 5.0 Design Tools
- 6.0 Packaging Information
MCP6271/1R/2/3/4/5
DS21810F-page 2 © 2008 Microchip Technology Inc.
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
V
DD
–V
SS
........................................................................7.0V
Current at Input Pins ....................................................±2 mA
Analog Inputs (V
IN
+ and V
IN
–) †† .. V
SS
–1.0VtoV
DD
+1.0V
All other Inputs and Outputs .......... V
SS
– 0.3V to V
DD
+0.3V
Difference Input Voltage ...................................... |V
DD
–V
SS
|
Output Short Circuit Current .................................Continuous
Current at Output and Supply Pins ............................±30 mA
Storage Temperature....................................–65°C to +150°C
Junction Temperature (T
J
) ..........................................+150°C
ESD Protection On All Pins (HBM/MM) ................ ≥ 4 kV/400V
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
†† See Section 4.1.2 “Input Voltage and Current Limits”.
DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, T
A
= +25°C, V
DD
= +2.0V to +5.5V, V
SS
= GND, V
CM
=V
DD
/2,
V
OUT
≈ V
DD
/2, V
L
= V
DD
/2, R
L
=10kΩ to V
L
and CS is tied low. (Refer to Figure 1-2 and Figure 1-3).
Parameters Sym Min Typ Max Units Conditions
Input Offset (Note 1)
Input Offset Voltage V
OS
–3.0 — +3.0 mV V
CM
= V
SS
Input Offset Voltage
(Extended Temperature)
V
OS
–5.0 — +5.0 mV T
A
= –40°C to +125°C, V
CM
= V
SS
Input Offset Temperature Drift ΔV
OS
/ΔT
A
—±1.7—µV/°CT
A
= –40°C to +125°C, V
CM
= V
SS
Power Supply Rejection Ratio PSRR 70 90 — dB V
CM
= V
SS
Input Bias Current and Impedance
Input Bias Current I
B
— ±1.0 — pA Note 2
At Temperature I
B
— 50 200 pA T
A
= +85°C (Note 2)
At Temperature I
B
—2 5nAT
A
= +125°C (Note 2)
Input Offset Current I
OS
— ±1.0 — pA Note 3
Common Mode Input Impedance Z
CM
—10
13
||6 — Ω||pF Note 3
Differential Input Impedance Z
DIFF
—10
13
||3 — Ω||pF Note 3
Common Mode (Note 4)
Common Mode Input Voltage Range V
CMR
V
SS
− 0.15 — V
DD
+0.15 V V
DD
= 2.0V (Note 5)
V
CMR
V
SS
− 0.30 — V
DD
+0.30 V V
DD
= 5.5V (Note 5)
Common Mode Rejection Ratio CMRR 70 85 — dB V
CM
= –0.3V to 2.5V, V
DD
= 5V
(Note 6)
Common Mode Rejection Ratio CMRR 65 80 — dB V
CM
= –0.3V to 5.3V, V
DD
= 5V
(Note 6)
Open-Loop Gain
DC Open-Loop Gain (Large Signal) A
OL
90 110 — dB V
OUT
= 0.2V to V
DD
– 0.2V,
V
CM
=V
SS
(Note 1)
Note 1: The MCP6275’s V
CM
for op amp B (pins V
OUTA
/V
INB
+ and V
INB
–) is V
SS
+100mV.
2: The current at the MCP6275’s V
INB
– pin is specified by I
B
only.
3: This specification does not apply to the MCP6275’s V
OUTA
/V
INB
+ pin.
4: The MCP6275’s V
INB
– pin (op amp B) has a common mode input voltage range (V
CMR
) of V
SS
+ 100 mV to
V
DD
– 100 mV. CMRR is not measured for op amp B of the MCP6275. The MCP6275’s V
OUTA
/V
INB
+ pin (op amp B)
has a voltage range specified by V
OH
and V
OL
.
5: Set by design and characterization.
6: Does not apply to op amp B of the MCP6275.
7: All parts with date codes November 2007 and later have been screened to ensure operation at V
DD
= 6.0V. However,
the other minimum and maximum specifications are measured at 2.0V and 5.5V.