Datasheet
Table Of Contents
- 1.0 Electrical Characteristics
- 2.0 Typical Performance Curves
- FIGURE 2-1: Input Offset Voltage.
- FIGURE 2-2: Input Bias Current at TA = +85˚C.
- FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage, with VDD = 2.0V.
- FIGURE 2-4: Input Offset Voltage Drift.
- FIGURE 2-5: Input Bias Current at TA = +125˚C.
- FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage, with VDD = 5.5V.
- FIGURE 2-7: Common Mode Input Voltage Range Lower Limit vs. Temperature.
- FIGURE 2-8: Input Offset Voltage vs. Output Voltage.
- FIGURE 2-9: CMRR, PSRR vs. Frequency.
- FIGURE 2-10: Common Mode Input Voltage Range Upper Limit vs. Temperature.
- FIGURE 2-11: Input Bias, Input Offset Currents vs. Temperature.
- FIGURE 2-12: CMRR, PSRR vs. Temperature.
- FIGURE 2-13: Input Bias, Offset Currents vs. Common Mode Input Voltage, with TA = +85˚C.
- FIGURE 2-14: Quiescent Current vs. Supply Voltage.
- FIGURE 2-15: Open-Loop Gain, Phase vs. Frequency.
- FIGURE 2-16: Input Bias, Offset Currents vs. Common Mode Input Voltage, with TA = +125˚C.
- FIGURE 2-17: Output Voltage Headroom vs. Output Current Magnitude.
- FIGURE 2-18: Gain Bandwidth Product, Phase Margin vs. Temperature.
- FIGURE 2-19: Maximum Output Voltage Swing vs. Frequency.
- FIGURE 2-20: Input Noise Voltage Density vs. Frequency.
- FIGURE 2-21: Output Short Circuit Current vs. Supply Voltage.
- FIGURE 2-22: Slew Rate vs. Temperature.
- FIGURE 2-23: Input Noise Voltage Density vs. Common Mode Input Voltage, with f = 1 kHz.
- FIGURE 2-24: Channel-to-Channel Separation vs. Frequency (MCP6272 and MCP6274).
- FIGURE 2-25: Quiescent Current vs. Chip Select (CS) Voltage, with VDD = 2.0V (MCP6273 and MCP6275 only).
- FIGURE 2-26: Large Signal Non-inverting Pulse Response.
- FIGURE 2-27: Small Signal Non-inverting Pulse Response.
- FIGURE 2-28: Quiescent Current vs. Chip Select (CS) Voltage, with VDD = 5.5V (MCP6273 and MCP6275 only).
- FIGURE 2-29: Large Signal Inverting Pulse Response.
- FIGURE 2-30: Small Signal Inverting Pulse Response.
- FIGURE 2-31: Chip Select (CS) to Amplifier Output Response Time, with VDD = 2.0V (MCP6273 and MCP6275 only).
- FIGURE 2-32: Input Current vs. Input Voltage.
- FIGURE 2-33: Chip Select (CS) to Amplifier Output Response Time, with VDD = 5,5V (MCP6273 and MCP6275 only).
- FIGURE 2-34: The MCP6271/1R/2/3/4/5 Show no Phase Reversal.
- 3.0 Pin Descriptions
- 4.0 Application Information
- 4.1 Rail-to-Rail Inputs
- 4.2 Rail-to-Rail Output
- 4.3 Capacitive Loads
- 4.4 MCP6273/5 Chip Select
- 4.5 Cascaded Dual Op Amps (MCP6275)
- 4.6 Unused Amplifiers
- 4.7 Supply Bypass
- 4.8 PCB Surface Leakage
- 4.9 Application Circuits
- FIGURE 4-8: Active Full-wave Rectifier.
- FIGURE 4-9: Non-Inverting Integrator.
- FIGURE 4-10: Isolating the Load with a Buffer.
- FIGURE 4-11: Cascaded Gain Circuit Configuration.
- FIGURE 4-12: Difference Amplifier Circuit.
- FIGURE 4-13: Integrator Circuit with Active Compensation.
- FIGURE 4-14: Second Order Multiple Feedback Low-Pass Filter with an Extra Pole- Zero Pair.
- FIGURE 4-15: Second Order Sallen-Key Low-Pass Filter with an Extra Pole-Zero Pair and Chip Select.
- FIGURE 4-16: Capacitorless Second Order Low-Pass Filter with Chip Select.
- 5.0 Design Tools
- 6.0 Packaging Information
MCP6271/1R/2/3/4/5
DS21810F-page 14 © 2008 Microchip Technology Inc.
4.3 Capacitive Loads
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. A unity gain buffer (G = +1) is the most
sensitive to capacitive loads, though all gains show the
same general behavior.
When driving large capacitive loads with these op
amps (e.g., > 100 pF when G = +1), a small series
resistor at the output (R
ISO
in Figure 4-3) improves the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will be generally lower than the bandwidth
with no capacitive load.
FIGURE 4-3: Output Resistor, R
ISO
stabilizes large capacitive loads.
Figure 4-4 gives recommended R
ISO
values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (C
L
/G
N
), where G
N
is the
circuit's noise gain. For non-inverting gains, G
N
and the
Signal Gain are equal. For inverting gains, G
N
is
1+|Signal Gain| (e.g., –1 V/V gives G
N
= +2 V/V).
FIGURE 4-4: Recommended R
ISO
Values
for Capacitive Loads.
After selecting R
ISO
for your circuit, double check the
resulting frequency response peaking and step
response overshoot. Modify R
ISO
's value until the
response is reasonable. Bench evaluation and
simulations with the MCP6271/1R/2/3/4/5 SPICE
macro model are helpful.
4.4 MCP6273/5 Chip Select
The MCP6273 and MCP6275 are single and dual op
amps with Chip Select (CS
), respectively. When CS is
pulled high, the supply current drops to 0.7 µA (typical)
and flows through the CS pin to V
SS
. When this
happens, the amplifier output is put into a high
impedance state. By pulling CS
low, the amplifier is
enabled. The CS
pin has an internal 5 MΩ (typical) pull-
down resistor connected to V
SS
, so it will go low if the
CS pin is left floating. Figure 1-1 shows the output volt-
age and supply current response to a CS
pulse.
4.5 Cascaded Dual Op Amps
(MCP6275)
The MCP6275 is a dual op amp with Chip Select (CS).
The Chip Select input is available on what would be the
non-inverting input of a standard dual op amp (pin 5).
This pin is available because the output of op amp A
connects to the non-inverting input of op amp B, as
shown in Figure 4-5. The Chip Select input, which can
be connected to a microcontroller I/O line, puts the
device in low power mode. Refer to Section 4.4
“MCP6273/5 Chip Select (CS
)”.
FIGURE 4-5: Cascaded Gain Amplifier.
The output of op amp A is loaded by the input
impedance of op amp B, which is typically
10
13
Ω⎟⎟6 pF, as specified in the DC specification table
(Refer to Section 4.3 “Capacitive Loads” for further
details regarding capacitive loads).
The common mode input range of these op amps is
specified in the data sheet as V
SS
– 300 mV and
V
DD
+ 300 mV. However, since the output of op amp A
is limited to V
OL
and V
OH
(20 mV from the rails with a
10 kΩ load), the non-inverting input range of op amp B
is limited to the common mode input range of
V
SS
+ 20 mV and V
DD
–20mV.
V
IN
R
ISO
V
OUT
C
L
–
+
MCP627X
10
100
1,000
10 100 1,000 10,000
Normalized Load Capacitance; C
L
/ G
N
(pF)
Recommended R
ISO
(
:
)
G
N
= 1 V/V
G
N
= 2 V/V
G
N
t 4 V/V
A
B
CS
2
3
5
6
7
V
INA
+
V
OUTB
MCP6275
1
V
INA
–
V
OUTA
/V
INB
+
V
INB
–