Datasheet
Table Of Contents
- 1.0 Electrical Characteristics
- 2.0 Typical Performance Curves
- FIGURE 2-1: Input Offset Voltage.
- FIGURE 2-2: Input Bias Current at TA = +85˚C.
- FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage, with VDD = 2.0V.
- FIGURE 2-4: Input Offset Voltage Drift.
- FIGURE 2-5: Input Bias Current at TA = +125˚C.
- FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage, with VDD = 5.5V.
- FIGURE 2-7: Common Mode Input Voltage Range Lower Limit vs. Temperature.
- FIGURE 2-8: Input Offset Voltage vs. Output Voltage.
- FIGURE 2-9: CMRR, PSRR vs. Frequency.
- FIGURE 2-10: Common Mode Input Voltage Range Upper Limit vs. Temperature.
- FIGURE 2-11: Input Bias, Input Offset Currents vs. Temperature.
- FIGURE 2-12: CMRR, PSRR vs. Temperature.
- FIGURE 2-13: Input Bias, Offset Currents vs. Common Mode Input Voltage, with TA = +85˚C.
- FIGURE 2-14: Quiescent Current vs. Supply Voltage.
- FIGURE 2-15: Open-Loop Gain, Phase vs. Frequency.
- FIGURE 2-16: Input Bias, Offset Currents vs. Common Mode Input Voltage, with TA = +125˚C.
- FIGURE 2-17: Output Voltage Headroom vs. Output Current Magnitude.
- FIGURE 2-18: Gain Bandwidth Product, Phase Margin vs. Temperature.
- FIGURE 2-19: Maximum Output Voltage Swing vs. Frequency.
- FIGURE 2-20: Input Noise Voltage Density vs. Frequency.
- FIGURE 2-21: Output Short Circuit Current vs. Supply Voltage.
- FIGURE 2-22: Slew Rate vs. Temperature.
- FIGURE 2-23: Input Noise Voltage Density vs. Common Mode Input Voltage, with f = 1 kHz.
- FIGURE 2-24: Channel-to-Channel Separation vs. Frequency (MCP6272 and MCP6274).
- FIGURE 2-25: Quiescent Current vs. Chip Select (CS) Voltage, with VDD = 2.0V (MCP6273 and MCP6275 only).
- FIGURE 2-26: Large Signal Non-inverting Pulse Response.
- FIGURE 2-27: Small Signal Non-inverting Pulse Response.
- FIGURE 2-28: Quiescent Current vs. Chip Select (CS) Voltage, with VDD = 5.5V (MCP6273 and MCP6275 only).
- FIGURE 2-29: Large Signal Inverting Pulse Response.
- FIGURE 2-30: Small Signal Inverting Pulse Response.
- FIGURE 2-31: Chip Select (CS) to Amplifier Output Response Time, with VDD = 2.0V (MCP6273 and MCP6275 only).
- FIGURE 2-32: Input Current vs. Input Voltage.
- FIGURE 2-33: Chip Select (CS) to Amplifier Output Response Time, with VDD = 5,5V (MCP6273 and MCP6275 only).
- FIGURE 2-34: The MCP6271/1R/2/3/4/5 Show no Phase Reversal.
- 3.0 Pin Descriptions
- 4.0 Application Information
- 4.1 Rail-to-Rail Inputs
- 4.2 Rail-to-Rail Output
- 4.3 Capacitive Loads
- 4.4 MCP6273/5 Chip Select
- 4.5 Cascaded Dual Op Amps (MCP6275)
- 4.6 Unused Amplifiers
- 4.7 Supply Bypass
- 4.8 PCB Surface Leakage
- 4.9 Application Circuits
- FIGURE 4-8: Active Full-wave Rectifier.
- FIGURE 4-9: Non-Inverting Integrator.
- FIGURE 4-10: Isolating the Load with a Buffer.
- FIGURE 4-11: Cascaded Gain Circuit Configuration.
- FIGURE 4-12: Difference Amplifier Circuit.
- FIGURE 4-13: Integrator Circuit with Active Compensation.
- FIGURE 4-14: Second Order Multiple Feedback Low-Pass Filter with an Extra Pole- Zero Pair.
- FIGURE 4-15: Second Order Sallen-Key Low-Pass Filter with an Extra Pole-Zero Pair and Chip Select.
- FIGURE 4-16: Capacitorless Second Order Low-Pass Filter with Chip Select.
- 5.0 Design Tools
- 6.0 Packaging Information
© 2008 Microchip Technology Inc. DS21810F-page 13
MCP6271/1R/2/3/4/5
4.0 APPLICATION INFORMATION
The MCP6271/1R/2/3/4/5 family of op amps is
manufactured using Microchip’s state of the art CMOS
process, specifically designed for low cost, low power
and general purpose applications. The low supply
voltage, low quiescent current and wide bandwidth
make the MCP6271/1R/2/3/4/5 ideal for battery
powered applications.
4.1 Rail-to-Rail Inputs
4.1.1 PHASE REVERSAL
The input devices are designed to not exhibit phase
inversion when the input pins exceed the supply
voltages. Figure 2-34 shows an input voltage
exceeding both supplies with no phase inversion.
4.1.2 INPUT VOLTAGE AND CURRENT
LIMITS
The ESD protection on the inputs can be depicted as
shown in Figure 4-1. This structure was chosen to
protect the input transistors, and to minimize input bias
current (I
B
). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
V
SS
. They also clamp any voltages that go too far
above V
DD
; their breakdown voltage is high enough to
allow normal operation, and low enough to bypass
quick ESD events within the specified limits.
FIGURE 4-1: Simplified Analog Input ESD
Structures.
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the currents
(and voltages) at the input pins (see Absolute Maxi-
mum Ratings † at the beginning of Section 1.0 “Elec-
trical Characteristics”). Figure 4-2 shows the
recommended approach to protecting these inputs.
The internal ESD diodes prevent the input pins (V
IN
+
and V
IN
–) from going too far below ground, and the
resistors R
1
and R
2
limit the possible current drawn out
of the input pins. Diodes D
1
and D
2
prevent the input
pins (V
IN
+ and V
IN
–) from going too far above V
DD
, and
dump any currents onto V
DD
. When implemented as
shown, resistors R
1
and R
2
also limit the current
through D
1
and D
2
.
FIGURE 4-2: Protecting the Analog
Inputs.
It is also possible to connect the diodes to the left of the
resistor R
1
and R
2
. In this case, the currents through
the diodes D
1
and D
2
need to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (V
IN
+ and
V
IN
–) should be very small.
A significant amount of current can flow out of the
inputs (through the ESD diodes) when the common
mode voltage (V
CM
) is below ground (V
SS
); see
Figure 2-32. Applications that are high impedance may
need to limit the usable voltage range.
4.1.3 NORMAL OPERATIONS
The input stage of the MCP6271/1R/2/3/4/5 op amps
uses two differential CMOS input stages in parallel.
One operates at low common mode input voltage (V
CM
and the other at high V
CM
. With this topology, the input
operates with V
CM
up to 0.3V past either supply rail
(see Figure 2-7 and Figure 2-10). The input offset volt-
age (V
OS
) is measured at V
CM
=V
SS
–0.3V and
V
DD
+ 0.3V to ensure proper operation.
The transition between the two input stage occurs
when V
CM
≈ V
DD
–1.1V (see Figure 2-3 and Figure 2-
6). For the best distortion and gain linearity, with non-
inverting gains, avoid this region of operation.
4.2 Rail-to-Rail Output
The output voltage range of the MCP6271/1R/2/3/4/5
op amps is V
DD
– 15 mV (minimum) and V
SS
+15mV
(maximum) when R
L
=10kΩ is connected to V
DD
/2
and V
DD
= 5.5V. Refer to Figure 2-17 for more informa-
tion.
Bond
Pad
Bond
Pad
Bond
Pad
V
DD
V
IN
+
V
SS
Input
Stage
Bond
Pad
V
IN
–
V
1
MCP627X
R
1
V
DD
D
1
R
1
>
V
SS
– (minimum expected V
1
)
2mA
V
OUT
R
2
>
V
SS
– (minimum expected V
2
)
2mA
V
2
R
2
D
2
R
3