Datasheet
Table Of Contents
- 1.0 Electrical Characteristics
- 2.0 Typical Performance Curves
- FIGURE 2-1: Input Offset Voltage.
- FIGURE 2-2: Input Bias Current at TA = +85˚C.
- FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage, with VDD = 2.0V.
- FIGURE 2-4: Input Offset Voltage Drift.
- FIGURE 2-5: Input Bias Current at TA = +125˚C.
- FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage, with VDD = 5.5V.
- FIGURE 2-7: Common Mode Input Voltage Range Lower Limit vs. Temperature.
- FIGURE 2-8: Input Offset Voltage vs. Output Voltage.
- FIGURE 2-9: CMRR, PSRR vs. Frequency.
- FIGURE 2-10: Common Mode Input Voltage Range Upper Limit vs. Temperature.
- FIGURE 2-11: Input Bias, Input Offset Currents vs. Temperature.
- FIGURE 2-12: CMRR, PSRR vs. Temperature.
- FIGURE 2-13: Input Bias, Offset Currents vs. Common Mode Input Voltage, with TA = +85˚C.
- FIGURE 2-14: Quiescent Current vs. Supply Voltage.
- FIGURE 2-15: Open-Loop Gain, Phase vs. Frequency.
- FIGURE 2-16: Input Bias, Offset Currents vs. Common Mode Input Voltage, with TA = +125˚C.
- FIGURE 2-17: Output Voltage Headroom vs. Output Current Magnitude.
- FIGURE 2-18: Gain Bandwidth Product, Phase Margin vs. Temperature.
- FIGURE 2-19: Maximum Output Voltage Swing vs. Frequency.
- FIGURE 2-20: Input Noise Voltage Density vs. Frequency.
- FIGURE 2-21: Output Short Circuit Current vs. Supply Voltage.
- FIGURE 2-22: Slew Rate vs. Temperature.
- FIGURE 2-23: Input Noise Voltage Density vs. Common Mode Input Voltage, with f = 1 kHz.
- FIGURE 2-24: Channel-to-Channel Separation vs. Frequency (MCP6272 and MCP6274).
- FIGURE 2-25: Quiescent Current vs. Chip Select (CS) Voltage, with VDD = 2.0V (MCP6273 and MCP6275 only).
- FIGURE 2-26: Large Signal Non-inverting Pulse Response.
- FIGURE 2-27: Small Signal Non-inverting Pulse Response.
- FIGURE 2-28: Quiescent Current vs. Chip Select (CS) Voltage, with VDD = 5.5V (MCP6273 and MCP6275 only).
- FIGURE 2-29: Large Signal Inverting Pulse Response.
- FIGURE 2-30: Small Signal Inverting Pulse Response.
- FIGURE 2-31: Chip Select (CS) to Amplifier Output Response Time, with VDD = 2.0V (MCP6273 and MCP6275 only).
- FIGURE 2-32: Input Current vs. Input Voltage.
- FIGURE 2-33: Chip Select (CS) to Amplifier Output Response Time, with VDD = 5,5V (MCP6273 and MCP6275 only).
- FIGURE 2-34: The MCP6271/1R/2/3/4/5 Show no Phase Reversal.
- 3.0 Pin Descriptions
- 4.0 Application Information
- 4.1 Rail-to-Rail Inputs
- 4.2 Rail-to-Rail Output
- 4.3 Capacitive Loads
- 4.4 MCP6273/5 Chip Select
- 4.5 Cascaded Dual Op Amps (MCP6275)
- 4.6 Unused Amplifiers
- 4.7 Supply Bypass
- 4.8 PCB Surface Leakage
- 4.9 Application Circuits
- FIGURE 4-8: Active Full-wave Rectifier.
- FIGURE 4-9: Non-Inverting Integrator.
- FIGURE 4-10: Isolating the Load with a Buffer.
- FIGURE 4-11: Cascaded Gain Circuit Configuration.
- FIGURE 4-12: Difference Amplifier Circuit.
- FIGURE 4-13: Integrator Circuit with Active Compensation.
- FIGURE 4-14: Second Order Multiple Feedback Low-Pass Filter with an Extra Pole- Zero Pair.
- FIGURE 4-15: Second Order Sallen-Key Low-Pass Filter with an Extra Pole-Zero Pair and Chip Select.
- FIGURE 4-16: Capacitorless Second Order Low-Pass Filter with Chip Select.
- 5.0 Design Tools
- 6.0 Packaging Information
MCP6271/1R/2/3/4/5
DS21810F-page 12 © 2008 Microchip Technology Inc.
3.0 PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1 (single op amps) and Table 3-2 (dual and quad op amps).
TABLE 3-1: PIN FUNCTION TABLE FOR SINGLE OP AMPS
TABLE 3-2: PIN FUNCTION TABLE FOR DUAL AND QUAD OP AMPS
3.1 Analog Outputs
The output pins are low impedance voltage sources.
3.2 Analog Inputs
The non-inverting and inverting inputs are high
impedance CMOS inputs with low bias currents.
3.3 MCP6275’s V
OUTA
/V
INB
+ Pin
For the MCP6275 only, the output of op amp A is
connected directly to the non-inverting input of op amp
B; this is the V
OUTA
/V
INB
+ pin. This connection makes
it possible to provide a CS
pin for duals in 8-pin
packages.
3.4 Chip Select Digital Input
This is a CMOS, Schmitt triggered input that places the
part into a low power mode of operation.
3.5 Power Supply Pins
The positive power supply (V
DD
) is 2.0V to 6.0V higher
than the negative power supply (V
SS
). For normal
operation, the other pins are at voltages between V
SS
and V
DD
.
Typically, these parts are used in a single (positive)
supply configuration. In this case, V
SS
is connected to
ground and V
DD
is connected to the supply. V
DD
will
need bypass capacitors.
MCP6271 MCP6271R MCP6273
Symbol Description
PDIP, SOIC,
MSOP
SOT-23-5 SOT-23-5
PDIP, SOIC,
MSOP
SOT-23-6
244 24V
IN
– Inverting Input
333 33V
IN
+ Non-inverting Input
425 42V
SS
Negative Power Supply
611 61V
OUT
Analog Output
752 76V
DD
Positive Power Supply
——— 8 5CS
Chip Select
1,5,8 — — 1,5 — NC No Internal Connection
MCP6272 MCP6274 MCP6275 Symbol Description
11—V
OUTA
Analog Output (op amp A)
222V
INA
– Inverting Input (op amp A)
333V
INA
+ Non-inverting Input (op amp A)
848 V
DD
Positive Power Supply
55—V
INB
+ Non-inverting Input (op amp B)
666V
INB
– Inverting Input (op amp B)
777V
OUTB
Analog Output (op amp B)
—8—V
OUTC
Analog Output (op amp C)
—9—V
INC
– Inverting Input (op amp C)
—10— V
INC
+ Non-inverting Input (op amp C)
4114 V
SS
Negative Power Supply
—12— V
IND
+ Non-inverting Input (op amp D)
—13— V
IND
– Inverting Input (op amp D)
—14— V
OUTD
Analog Output (op amp D)
—— 1V
OUTA
/V
INB
+ Analog Output (op amp A)/Non-inverting Input (op amp B)
—— 5 CS
Chip Select