MCP6271/1R/2/3/4/5 170 µA, 2 MHz Rail-to-Rail Op Amp Features Description • • • • • • • The Microchip Technology Inc. MCP6271/1R/2/3/4/5 family of operational amplifiers (op amps) provide wide bandwidth for the current. This family has a 2 MHz Gain Bandwidth Product (GBWP) and a 65° Phase Margin. This family also operates from a single supply voltage as low as 2.0V, while drawing 170 µA (typical) quiescent current.
MCP6271/1R/2/3/4/5 1.0 ELECTRICAL CHARACTERISTICS VDD – VSS ........................................................................7.0V † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied.
MCP6271/1R/2/3/4/5 DC ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2, VL = VDD/2, RL = 10 kΩ to VL and CS is tied low. (Refer to Figure 1-2 and Figure 1-3). Parameters Sym Min Typ Max Units VOL, VOH VSS + 15 — VDD − 15 mV ISC — ±25 — mA Conditions Output Maximum Output Voltage Swing Output Short Circuit Current 0.
MCP6271/1R/2/3/4/5 TEMPERATURE SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, VDD = +2.0V to +5.5V and VSS = GND.
MCP6271/1R/2/3/4/5 1.1 Test Circuits The test circuits used for the DC and AC tests are shown in Figure 1-2 and Figure 1-3. The bypass capacitors are laid out according to the rules discussed in Section 4.7 “Supply Bypass”. VDD VIN RN 0.1 µF 1 µF VOUT MCP627X CL VDD/2 RG RL RF VL FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. VDD VDD/2 RN 0.1 µF 1 µF VOUT MCP627X CL VIN RG RL RF VL FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions.
MCP6271/1R/2/3/4/5 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
MCP6271/1R/2/3/4/5 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2, 0.00 -0.05 -0.10 -0.15 -0.20 -0.25 -0.30 -0.35 -0.40 -0.45 -0.50 Common Mode Input Voltage Range Limit (V) Common Mode Input Voltage Range Limit (V) VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS is tied low. Typical lower (VCM – VSS) limit VDD = 2.0V VDD = 5.5V -50 -25 0 25 50 75 100 Ambient Temperature (°C) 125 FIGURE 2-7: Common Mode Input Voltage Range Lower Limit vs.
MCP6271/1R/2/3/4/5 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS is tied low. 2.5 Input Bias, Offset Currents (nA) 45 Input Bias Current 35 25 15 5 Input Offset Current -5 TA = 85°C VDD = 5.5V -15 -25 2.0 1.5 0.5 0.0 -1.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Common Mode Input Voltage (V) FIGURE 2-16: Input Bias, Offset Currents vs. Common Mode Input Voltage, with TA = +125°C.
MCP6271/1R/2/3/4/5 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS is tied low. 1.8 1.6 VDD = 5.5V Slew Rate (V/µs) VDD = 2.0V 1 Frequency (Hz) 1M 1.E+07 100k 1.E+06 10k 1.E+05 1.2 1.0 0.8 VDD = 2.0V 0.6 Rising Edge 0.4 0.0 10M FIGURE 2-19: Maximum Output Voltage Swing vs. Frequency.
MCP6271/1R/2/3/4/5 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS is tied low. 700 250 Op Amp turns Off Op Amp turns On 150 Hysteresis 100 50 CS swept High-to-Low CS swept Low-to-High VDD = 5.5V 600 Hysteresis 500 CS swept Low-to-High 400 CS swept High-to-Low 200 Quiescent Current (µA/amplifier) Quiescent Current (µA/amplifier) VDD = 2.0V 300 200 100 0 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.
MCP6271/1R/2/3/4/5 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS is tied low. 2.0 CS VDD = 2.0V G = +1 V/V VIN = VSS 1.5 Output On VOUT 1.0 0.5 Output High-Z 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 Chip Select, Output Voltages (V) Chip Select, Output Voltages (V) 2.5 0.0 Time (5 µs/div) FIGURE 2-31: Chip Select (CS) to Amplifier Output Response Time, with VDD = 2.
MCP6271/1R/2/3/4/5 3.0 PIN DESCRIPTIONS Descriptions of the pins are listed in Table 3-1 (single op amps) and Table 3-2 (dual and quad op amps).
MCP6271/1R/2/3/4/5 4.0 APPLICATION INFORMATION The MCP6271/1R/2/3/4/5 family of op amps is manufactured using Microchip’s state of the art CMOS process, specifically designed for low cost, low power and general purpose applications. The low supply voltage, low quiescent current and wide bandwidth make the MCP6271/1R/2/3/4/5 ideal for battery powered applications. dump any currents onto VDD. When implemented as shown, resistors R1 and R2 also limit the current through D1 and D2. VDD D1 V1 4.
MCP6271/1R/2/3/4/5 4.3 Capacitive Loads 4.4 Driving large capacitive loads can cause stability problems for voltage feedback op amps. As the load capacitance increases, the feedback loop’s phase margin decreases and the closed-loop bandwidth is reduced. This produces gain peaking in the frequency response, with overshoot and ringing in the step response. A unity gain buffer (G = +1) is the most sensitive to capacitive loads, though all gains show the same general behavior.
MCP6271/1R/2/3/4/5 4.6 Unused Amplifiers VIN– An unused op amp in a quad package (MCP6274) should be configured as shown in Figure 4-6. These circuits prevent the output from toggling and causing crosstalk. In Circuit A, R1 and R2 produce a voltage within its output voltage range (VOH, VOL). The op amp buffers this voltage, which can be used elsewhere in the circuit. Circuit B uses the minimum number of components and operates as a comparator.
MCP6271/1R/2/3/4/5 4.9 Application Circuits 4.9.1 4.9.2 ACTIVE FULL-WAVE RECTIFIER The MCP6271/1R/2/3/4/5 family of amplifiers can be used in applications such as an Active Full-Wave Rectifier or an Absolute Value circuit, as shown in Figure 4-8. The amplifier and feedback loops in this active voltage rectifier circuit eliminate the diode drop problem that exists in a passive voltage rectifier.
MCP6271/1R/2/3/4/5 4.9.3 CASCADED OP AMP APPLICATIONS R4 The MCP6275 provides the flexibility of Low power mode for dual op amps in an 8-pin package. The MCP6275 eliminates the added cost and space in a battery powered application by using two single op amps with Chip Select (CS) lines or a 10-pin device with one CS line for both op amps. Since the two op amps are internally cascaded, this device cannot be used in circuits that require active or passive elements between the two op amps.
MCP6271/1R/2/3/4/5 4.9.3.5 Second Order MFB with an Extra Pole-Zero Pair Figure 4-14 is a second order multiple feedback lowpass filter with Chip Select. Use the FilterLab® software from Microchip Technology Inc. to determine the R and C values for op amp A’s second order filter. Op amp B can be used to add a pole-zero pair using C3, R6 and R7. C3 R6 R7 R1 R3 R2 C1 R5 A VOUT B VIN 4.9.3.
MCP6271/1R/2/3/4/5 5.0 DESIGN TOOLS Microchip provides the basic design tools needed for the MCP6271/1R/2/3/4/5 family of op amps. 5.1 SPICE Macro Model The latest SPICE macro model for the MCP6271/1R/2/ 3/4/5 op amps is available on the Microchip web site at www.microchip.com. This model is intended to be an initial design tool that works well in the op amp’s linear region of operation over the temperature range. See the model file for information on its capabilities.
MCP6271/1R/2/3/4/5 6.0 PACKAGING INFORMATION 6.
MCP6271/1R/2/3/4/5 Package Marking Information (Continued) 14-Lead PDIP (300 mil) (MCP6274) XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN Example: MCP6274-E/P 0437256 OR MCP6274 e3 E/P^^ 0644256 14-Lead SOIC (150 mil) (MCP6274) Example: XXXXXXXXXX XXXXXXXXXX YYWWNNN MCP6274ESL 0437256 OR MCP6274 e3 E/SL^^ 0644256 14-Lead TSSOP (MCP6274) XXXXXX YYWW NNN © 2008 Microchip Technology Inc.
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MCP6271/1R/2/3/4/5 APPENDIX A: REVISION HISTORY • Undocumented Changes Revision F (March 2008) Revision B (October 2003) The following is the list of modifications: 1. 2. 3. 4. Increased maximum operating VDD. Updated Section 5.0 “Design Tools” Various cleanups thoughout document. Updated package outline drawings Section 6.0 “Packaging Information” Revision C (June 2004) • Undocumented Changes Revision A (June 2003) in • Original data sheet release.
MCP6271/1R/2/3/4/5 NOTES: DS21810F-page 32 © 2008 Microchip Technology Inc.
MCP6271/1R/2/3/4/5 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO.
MCP6271/1R/2/3/4/5 NOTES: DS21810F-page 34 © 2008 Microchip Technology Inc.
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