Datasheet

MCP621/1S/2/3/4/5/9
DS22188C-page 24 © 2009-2011 Microchip Technology Inc.
When the V
CAL
pin is left open, the internal resistor
divider generates a V
CM_INT
of approximately V
DD
/3,
which is near the center of the input Common mode
voltage range. It is recommended that an external
capacitor from V
CAL
to ground be added to improve
noise immunity.
When the V
CAL
pin is driven by an external voltage
source, which is within its specified range, the op amp
will have its input offset voltage calibrated at that
Common mode input voltage. Make sure that V
CAL
is
within its specified range.
It is possible to use an external resistor voltage divider
to modify V
CM_INT
; see Figure 4-2. The internal circuitry
at the V
CAL
pin looks like 100 kΩ tied to V
DD
/3. The
parallel equivalent of R
1
and R
2
should be much
smaller than 100 kΩ to minimize differences in match-
ing and temperature drift between the internal and
external resistors. Again, make sure that V
CAL
is within
its specified range.
FIGURE 4-2: Setting V
CM
with External
Resistors.
For instance, a design goal to set V
CM_INT
=0.1V when
V
DD
= 2.5V could be met with: R
1
=24.3kΩ,
R
2
=1.00kΩ and C
1
= 100 nF. This will keep V
CAL
within its range for any V
DD
, and should be close
enough to 0V for ground-based applications.
4.2 Input
4.2.1 PHASE REVERSAL
The input devices are designed to not exhibit phase
inversion when the input pins exceed the supply
voltages. Figure 2-41 shows an input voltage
exceeding both supplies with no phase inversion.
4.2.2 INPUT VOLTAGE AND CURRENT
LIMITS
The ESD protection on the inputs can be depicted as
shown in Figure 4-3. This structure was chosen to
protect the input transistors, and to minimize input bias
current (I
B
). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
V
SS
. They also clamp any voltages that go too far
above V
DD
; their breakdown voltage is high enough to
allow normal operation, and low enough to bypass
quick ESD events within the specified limits.
FIGURE 4-3: Simplified Analog Input ESD
Structures.
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the currents
(and voltages) at the input pins (see Section 1.1
“Absolute Maximum Ratings †”). Figure 4-4 shows
the recommended approach to protecting these inputs.
The internal ESD diodes prevent the input pins (V
IN
+
and V
IN
–) from going too far below ground, and the
resistors R
1
and R
2
limit the possible current drawn out
of the input pins. Diodes D
1
and D
2
prevent the input
pins (V
IN
+ and V
IN
–) from going too far above V
DD
, and
dump any currents onto V
DD
. When implemented as
shown, resistors R
1
and R
2
also limit the current
through D
1
and D
2
.
FIGURE 4-4: Protecting the Analog
Inputs.
It is also possible to connect the diodes to the left of the
resistor R
1
and R
2
. In this case, the currents through
the diodes D
1
and D
2
need to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (V
IN
+ and
V
IN
–) should be very small.
R
1
R
2
V
SS
V
DD
V
CAL
C
1
MCP62X
Bond
Pad
Bond
Pad
Bond
Pad
V
DD
V
IN
+
V
SS
Input
Stage
Bond
Pad
V
IN
–
V
1
R
1
V
DD
D
1
R
1
>
V
SS
– (minimum expected V
1
)
2mA
V
OUT
R
2
>
V
SS
– (minimum expected V
2
)
2mA
V
2
R
2
D
2
MCP62X