Datasheet

© 2009-2011 Microchip Technology Inc. DS22188C-page 3
MCP621/1S/2/3/4/5/9
1.0 ELECTRICAL CHARACTERISTICS
1.1 Absolute Maximum Ratings †
V
DD
–V
SS
.......................................................................6.5V
Current at Input Pins ....................................................±2 mA
Analog Inputs (V
IN
+ and V
IN
–) †† . V
SS
– 1.0V to V
DD
+1.0V
All Other Inputs and Outputs ......... V
SS
– 0.3V to V
DD
+0.3V
Output Short Circuit Current ................................ Continuous
Current at Output and Supply Pins ..........................±150 mA
Storage Temperature ...................................-65°C to +150°C
Max. Junction Temperature ........................................+150°C
ESD protection on all pins (HBM, MM) ................≥ 1 kV, 200V
†Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at those or any other
conditions above those indicated in the operational
listings of this specification is not implied. Exposure to
maximum rating conditions for extended periods may
affect device reliability.
†† See Section 4.2.2, Input Voltage and Current
Limits.
1.2 Specifications
TABLE 1-1: DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, T
A
= +25°C, V
DD
= +2.5V to +5.5V, V
SS
= GND,
V
CM
= V
DD
/3, V
OUT
≈ V
DD
/2, V
L
= V
DD
/2, R
L
= 2 kΩ to V
L
and CAL/CS =V
SS
(refer to Figure 1-2).
Parameters Sym Min Typ Max Units Conditions
Input Offset
Input Offset Voltage V
OS
-200 — +200 µV After calibration (Note 1)
Input Offset Voltage Trim Step
Size
V
OSTRM
—37200µV(Note 2)
Input Offset Voltage Drift ΔV
OS
/ΔT
A
—±2.0—µV/°CT
A
= -40°C to +125°C
Power Supply Rejection Ratio PSRR 61 76 — dB
Input Current and Impedance
Input Bias Current I
B
—5—pA
Across Temperature I
B
—100—pAT
A
= +85°C
Across Temperature I
B
— 1700 5,000 pA T
A
= +125°C
Input Offset Current I
OS
—±10—pA
Common Mode Input
Impedance
Z
CM
—10
13
||9 — Ω||pF
Differential Input Impedance Z
DIFF
—10
13
||2 — Ω||pF
Common Mode
Common Mode Input Voltage
Range
V
CMR
V
SS
− 0.3 — V
DD
− 1.3 V (Note 3)
Common Mode Rejection Ratio CMRR 65 81 — dB V
DD
= 2.5V, V
CM
= -0.3 to
1.2V
CMRR 68 84 — dB V
DD
= 5.5V, V
CM
= -0.3 to
4.2V
Open-Loop Gain
DC Open-Loop Gain
(large signal)
A
OL
88 117 — dB V
DD
= 2.5V,
V
OUT
= 0.3V to 2.2V
A
OL
94 126 — dB V
DD
= 5.5V,
V
OUT
= 0.3V to 5.2V
Note 1: Describes the offset (under the specified conditions) right after power-up, or just after the CAL/CS
pin is
toggled. Thus, 1/f noise effects (an apparent wander in V
OS
; see Figure 2-35) are not included.
2: Increment between adjacent V
OS
trim points; Figure 2-3 shows how this affects the V
OS
repeatability.
3: See Figure 2-6 and Figure 2-7 for temperature effects.
4: The I
SC
specifications are for design guidance only; they are not tested.