Datasheet
© 2009-2011 Microchip Technology Inc. DS22188C-page 25
MCP621/1S/2/3/4/5/9
A significant amount of current can flow out of the
inputs (through the ESD diodes) when the Common
mode voltage (V
CM
) is below ground (V
SS
); see
Figure 2-15. Applications that are high-impedance may
need to limit the usable voltage range.
4.2.3 NORMAL OPERATION
The input stage of the MCP621/1S/2/3/4/5/9 op amps
use a differential PMOS input stage. It operates at low
Common mode input voltage (V
CM
), with V
CM
up to
V
DD
– 1.3V and down to V
SS
– 0.3V. The input offset
voltage (V
OS
) is measured at V
CM
=V
SS
–0.3V and
V
DD
– 1.3V to ensure proper operation. See Figure 2-6
and Figure 2-7 for temperature effects.
When operating at very low non-inverting gains, the
output voltage is limited at the top by the V
CM
range
(< V
DD
–1.3V); see Figure 4-5.
FIGURE 4-5: Unity Gain Voltage
Limitations for Linear Operation.
4.3 Rail-to-Rail Output
4.3.1 MAXIMUM OUTPUT VOLTAGE
The Maximum Output Voltage (see Figure 2-16 and
Figure 2-17) describes the output range for a given
load. For instance, the output voltage swings to within
40 mV of the negative rail with a 2 kΩ load tied to
V
DD
/2.
4.3.2 OUTPUT CURRENT
Figure 4-6 shows the possible combinations of output
voltage (V
OUT
) and output current (I
OUT
). I
OUT
is
positive when it flows out of the op amp into the
external circuit.
FIGURE 4-6: Output Current.
4.3.2.1 Power Dissipation
Since the output short circuit current (I
SC
) is specified
at ±70 mA (typical), these op amps are capable of both
delivering and dissipating significant power.
Two common loads, and their impact on the op amp’s
power dissipation, will be discussed.
Figure 4-7 shows a resistive load (R
L
) with a DC output
voltage (V
OUT
). V
L
is R
L
’s ground point, V
SS
is usually
ground (0V) and I
OUT
is the output current. The input
currents are assumed to be negligible.
FIGURE 4-7: Diagram for Resistive Load
Power Calculations.
The DC currents are:
EQUATION 4-1:
The DC op amp power is:
EQUATION 4-2:
The maximum op amp power, for resistive loads at DC,
occurs when V
OUT
is halfway between V
DD
and V
L
, or
halfway between V
SS
and V
L
:
EQUATION 4-3:
V
IN
V
DD
V
OUT
V
SS
V
<
IN
V
,
OUT
V
DD
1.3V–
≤
MCP62X
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
-80
-60
-40
-20
0
20
40
60
80
I
OUT
(mA)
V
OUT
(V)
R
L
= 10Ω
R
L
= 100
Ω
R
L
= 2 kΩ
V
OH
Limited
V
OL
Limited
-I
SC
Limited
+I
SC
Limited
(V
DD
= 5.5V)
V
DD
V
OUT
R
L
V
L
I
DD
I
SS
I
OUT
V
SS
MCP62X
I
OUT
V
OUT
V
L
–
R
L
--------------------------=
I
DD
I
Q
max 0 I
OUT
,()+
≈
I
SS
I–
Q
min 0 I
OUT
,()+
≈
Where:
I
Q
= Quiescent supply current for one op
amp (mA/amplifier)
V
OUT
= A DC value (V)
P
OA
I
DD
V
DD
V
OUT
–()I
SS
V
SS
V
OUT
–()+=
max P
OA
()I
DD
V
DD
V
SS
–()=
max
2
V
DD
V
L
– V
L
V
SS
–
,
()
4R
L
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