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MCP621/1S/2/3/4/5/9

Features

• Gain Bandwidth Product: 20 MHz (typical)

• Short Circuit Current: 70 mA (typical)

• Noise: 13 nV/√Hz (typical, at 1 MHz)

• Calibrated Input Offset: ±200 µV (maximum)

• Rail-to-Rail Output

• Slew Rate: 10 V/µs (typical)

• Supply Current: 2.5 mA (typical)

• Power Supply: 2.5V to 5.5V

• Extended Temperature Range: -40°C to +125°C

Typical Applications

• Driving A/D Converters

• Power Amplifier Control Loops

• Barcode Scanners

• Optical Detector Amplifier

Design Aids

• SPICE Macro Models

•FilterLab

Software

• Microchip Advanced Part Selector (MAPS)

• Analog Demonstration and Evaluation Boards

• Application Notes

Description

The Microchip Technology, Inc. MCP621/1S/2/3/4/5/9

family of operational amplifiers features low offset. At

power-up, these op amps are self-calibrated using

mCal. Some package options also provide a Calibra-

tion/Chip Select pin (CAL/CS

) that supports a Low-

Power mode of operation, with offset calibration at the

time normal operation is re-started. These amplifiers

are optimized for high speed, low noise and distortion,

single-supply operation with rail-to-rail output and an

input that includes the negative rail.

This family is offered in single (MCP621 and

MCP621S), single with CAL/CS

pin (MCP623), dual

(MCP622), dual with CAL/CS

pins (MCP625), quad

(MCP624) and quad with CAL/CS

pins (MCP629). All

devices are fully specified from -40°C to +125°C.

Typical Application Circuit

PowerDriverwithHighGain

OUT

MCP62X

20 MHz, 2.5 mA Op Amps with mCal

Summary of content (66 pages)

PAGE 1
MCP621/1S/2/3/4/5/9 20 MHz, 2.5 mA Op Amps with mCal Features Description • • • • • • • • • The Microchip Technology, Inc. MCP621/1S/2/3/4/5/9 family of operational amplifiers features low offset. At power-up, these op amps are self-calibrated using mCal. Some package options also provide a Calibration/Chip Select pin (CAL/CS) that supports a LowPower mode of operation, with offset calibration at the time normal operation is re-started.
PAGE 2
MCP621/1S/2/3/4/5/9 Package Types NC 1 8 CAL/CS VIN– 2 MCP621S SOT-23-5 MCP621 2x3 TDFN * MCP621 SOIC NC 1 VIN+ 3 7 VDD 6 VOUT VIN+ 3 VSS 4 5 VCAL VSS 4 8 CAL/CS VOUT 1 VIN– 2 EP 9 7 VDD VSS 6 VOUT 5 VCAL MCP624 SOIC, TSSOP 5 VDD 2 4 VIN- VIN+ 3 VOUTA 1 14 VOUTD VINA- 2 VINA+ 3 13 VIND12 VIND+ 11 VSS VDD 4 VINB+ 5 10 VINC+ VINB- 6 VOUTB 7 6 VINB– 5 VINB+ VINA+ 3 VSS 4 6 VINB– 5 VINB+ VSS 6 VDD 5 CAL/CS 2 4 VIN- VIN+ 3 VIND- VSS 4 7 VOUTB VINA– 2 8 VDD VOUT 1 7 VOUTB
PAGE 3
MCP621/1S/2/3/4/5/9 1.0 ELECTRICAL CHARACTERISTICS 1.1 Absolute Maximum Ratings † † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. VDD – VSS .......................
PAGE 4
MCP621/1S/2/3/4/5/9 TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/3, VOUT ≈ VDD/2, VL = VDD/2, RL = 2 kΩ to VL and CAL/CS = VSS (refer to Figure 1-2). Parameters Sym Min Typ Max Units Conditions Maximum Output Voltage Swing VOL, VOH VSS + 20 — VDD − 20 mV VDD = 2.5V, G = +2, 0.5V Input Overdrive VOL, VOH VSS + 40 — VDD − 40 mV VDD = 5.5V, G = +2, 0.
PAGE 5
MCP621/1S/2/3/4/5/9 TABLE 1-3: DIGITAL ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2, VL = VDD/2, RL = 2 kΩ to VL, CL = 50 pF and CAL/CS = VSS (refer to Figure 1-1 and Figure 1-2). Parameters Sym Min Typ Max Units Conditions CAL/CS Logic Threshold, Low VIL VSS — 0.2VDD V CAL/CS Input Current, Low ICSL — 0 — nA CAL/CS Logic Threshold, High VIH 0.
PAGE 6
MCP621/1S/2/3/4/5/9 TABLE 1-4: TEMPERATURE SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VDD = +2.5V to +5.5V,VSS = GND. Parameters Sym Min Typ Max Units Specified Temperature Range TA -40 — +125 °C Operating Temperature Range TA -40 — +125 °C Storage Temperature Range TA -65 — +150 °C Conditions Temperature Ranges (Note 1) Thermal Package Resistances Thermal Resistance, 5L-SOT-23 θJA — 220.
PAGE 7
MCP621/1S/2/3/4/5/9 1.4 Test Circuits The circuit used for most DC and AC tests is shown in Figure 1-2. This circuit can independently set VCM and VOUT; see Equation 1-1. Note that VCM is not the circuit’s Common mode voltage ((VP + VM)/2), and that VOST includes VOS plus the effects (on the input offset error, VOST) of temperature, CMRR, PSRR and AOL. CF 6.
PAGE 9
MCP621/1S/2/3/4/5/9 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
PAGE 10
MCP621/1S/2/3/4/5/9 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 2 kΩ to VL, CL = 50 pF, and CAL/CS = VSS. 1 Lot High (VDD – VCMR_H) 1.3 CMRR, PSRR (dB) High Input Common Mode Headroom (V) 1.4 V DD = 2.5V 1.2 1.1 V DD = 5.5V 1.0 -50 -25 0 25 50 75 100 Ambient Temperature (°C) CMRR, VDD = 2.5V -25 125 VDD = 5.5V 115 VDD = 2.
PAGE 11
MCP621/1S/2/3/4/5/9 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 2 kΩ to VL, CL = 50 pF, and CAL/CS = VSS. 1.E-03 1m Input Current Magnitude (A) IOS 100 100µ 1.E-04 80 10µ 1.E-05 60 1µ 1.E-06 Representative Part TA = +85°C VDD = 5.5V 40 20 100n 1.E-07 10n 1.E-08 0 -20 1n 1.E-09 100p 1.E-10 IB -40 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -60 -0.
PAGE 12
MCP621/1S/2/3/4/5/9 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 2 kΩ to VL, CL = 50 pF, and CAL/CS = VSS. Other DC Voltages and Currents 3.5 VDD = 5.5V 12 VOL – VSS -IOUT 3.0 Supply Current (mA/amplifier) 10 8 6 4 VDD – VOH IOUT VDD = 2.5V +125°C +85°C +25°C -40°C 1.0 RL = 2 kΩ 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 100 1.0 0.
PAGE 13
MCP621/1S/2/3/4/5/9 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, 25% 144 Samples VDD = 2.5V and 5.5V 20% 15% 10% 5% Normalized Internal Calibration Voltage; VCAL/VDD FIGURE 2-22: Normalized Internal Calibration Voltage. © 2009-2011 Microchip Technology Inc. 33.52% 33.48% 33.44% 33.40% 33.36% 33.32% 33.28% 33.24% 0% Internal V CAL Resistance (kΩ) 30% 33.
PAGE 14
MCP621/1S/2/3/4/5/9 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 2 kΩ to VL, CL = 50 pF, and CAL/CS = VSS. 0 120 -30 100 -60 ∠AOL -150 | AOL | -180 0 -210 -20 -240 35 25 25 GBWP 20 50 45 15 -50 -25 0 25 50 75 100 Ambient Temperature (°C) 40 125 FIGURE 2-26: Gain Bandwidth Product and Phase Margin vs. Ambient Temperature.
PAGE 15
MCP621/1S/2/3/4/5/9 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, 10 9 8 7 6 5 4 3 2 1 0 10p 1.0E-11 150 RS = 0Ω RS = 1 kΩ 140 GN = 1 V/V GN = 2 V/V GN ≥ 4 V/V Channel-to-Channel Separation (dB) Gain Peaking (dB) VL = VDD/2, RL = 2 kΩ to VL, CL = 50 pF, and CAL/CS = VSS. 130 120 110 100 90 80 70 60 100p 1n 1.0E-10 1.0E-09 Normalized Capacitive Load; CL/GN (F) FIGURE 2-30: Gain Peaking vs. Normalized Capacitive Load.
PAGE 16
MCP621/1S/2/3/4/5/9 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 2 kΩ to VL, CL = 50 pF, and CAL/CS = VSS. Input Noise and Distortion 1.E+4 10µ Input Offset + Noise; V OS + eni(t) (µV) 20 1.E+3 1µ 1.E+2 100n 15 Representative Part Analog NPBW = 0.1 Hz Sample Rate = 2 SPS 10 5 0 -5 -10 -15 -20 1.E+1 10n 0.1 1.E-1 1 1.E+0 10 1.E+1 FIGURE 2-32: vs. Frequency.
PAGE 17
MCP621/1S/2/3/4/5/9 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 2 kΩ to VL, CL = 50 pF, and CAL/CS = VSS. 2.5 Time Response 0 20 Output Voltage (V) VIN VOUT 40 60 Output Voltage (V) FIGURE 2-37: Step Response. 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 Non-inverting Small Signal VIN VOUT FIGURE 2-40: Response. 7 VDD = 5.
PAGE 18
MCP621/1S/2/3/4/5/9 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 2 kΩ to VL, CL = 50 pF, and CAL/CS = VSS. Maximum Output Voltage Swing (VP-P) 10 VDD = 5.5V VDD = 2.5V 1 0.1 100k 1.E+05 1M 10M 1.E+06 1.E+07 Frequency (Hz) 100M 1.E+08 FIGURE 2-43: Maximum Output Voltage Swing vs. Frequency. DS22188C-page 18 © 2009-2011 Microchip Technology Inc.
PAGE 19
MCP621/1S/2/3/4/5/9 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 2 kΩ to VL, CL = 50 pF, and CAL/CS = VSS. Calibration and Chip Select Response 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0.40 CAL/CS = VDD CAL/CS Hysteresis (V) CAL/CS Current (µA) 2.6 0.35 0.30 0.20 0.10 0.05 0.00 -50 VDD = 2.
PAGE 20
MCP621/1S/2/3/4/5/9 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 2 kΩ to VL, CL = 50 pF, and CAL/CS = VSS. 1.E-06 CAL/CS = VDD -1 Output Leakage Current (A) Negative Power Supply Current; I SS (µA) 0 -2 -3 -4 +125°C +85°C +25°C -40°C -5 -6 Power Supply Voltage (V) FIGURE 2-50: Quiescent Current in Shutdown vs. Power Supply Voltage. DS22188C-page 20 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.
PAGE 22
MCP621/1S/2/3/4/5/9 3.1 Analog Outputs The analog output pins (VOUT) are low-impedance voltage sources. 3.2 Analog Inputs The non-inverting and inverting inputs (VIN+, VIN–, …) are high-impedance CMOS inputs with low bias currents. 3.3 Power Supply Pins The positive power supply (VDD) is 2.5V to 5.5V higher than the negative power supply (VSS). For normal operation, the other pins are between VSS and VDD. Typically, these parts are used in a single (positive) supply configuration.
PAGE 23
MCP621/1S/2/3/4/5/9 4.0 APPLICATIONS The MCP621/1S/2/3/4/5/9 family of self-zeroed op amps is manufactured using Microchip’s state-of-theart CMOS process. It is designed for low-cost, lowpower and high-precision applications. Its low supply voltage, low quiescent current and wide bandwidth makes the MCP621/1S/2/3/4/5/9 ideal for batterypowered applications. 4.1 Calibration and Chip Select These op amps include circuitry for dynamic calibration of the offset voltage (VOS). 4.1.
PAGE 24
MCP621/1S/2/3/4/5/9 When the VCAL pin is left open, the internal resistor divider generates a VCM_INT of approximately VDD/3, which is near the center of the input Common mode voltage range. It is recommended that an external capacitor from VCAL to ground be added to improve noise immunity. When the VCAL pin is driven by an external voltage source, which is within its specified range, the op amp will have its input offset voltage calibrated at that Common mode input voltage.
PAGE 25
MCP621/1S/2/3/4/5/9 A significant amount of current can flow out of the inputs (through the ESD diodes) when the Common mode voltage (VCM) is below ground (VSS); see Figure 2-15. Applications that are high-impedance may need to limit the usable voltage range. 4.2.3 NORMAL OPERATION The input stage of the MCP621/1S/2/3/4/5/9 op amps use a differential PMOS input stage. It operates at low Common mode input voltage (VCM), with VCM up to VDD – 1.3V and down to VSS – 0.3V.
PAGE 26
MCP621/1S/2/3/4/5/9 Figure 4-7 shows a capacitive load (CL), which is driven by a sine wave with DC offset. The capacitive load causes the op amp to output higher currents at higher frequencies. Because the output rectifies IOUT, the op amp’s dissipated power increases (even though the capacitor does not dissipate power).
PAGE 27
MCP621/1S/2/3/4/5/9 4.4 Improving Stability 4.4.1 4.4.2 CAPACITIVE LOADS Driving large capacitive loads can cause stability problems for voltage feedback op amps. As the load capacitance increases, the feedback loop’s phase margin decreases and the closed-loop bandwidth is reduced. This produces gain peaking in the frequency response, with overshoot and ringing in the step response. See Figure 2-30.
PAGE 28
MCP621/1S/2/3/4/5/9 It is also possible to add a capacitor (CF) in parallel with RF to compensate for the destabilizing effect of CG. This makes it possible to use larger values of RF. The conditions for stability are summarized in Equation 4-10. EQUATION 4-10: Given: G N1 = 1 + R F ⁄ R G G N2 = 1 + C G ⁄ C F fF = 1 ⁄ ( 2 π RF CF ) f Z = f F ( G N1 ⁄ G N2 ) We need: f F ≤ f GBWP ⁄ ( 2G N2 ) , G N1 < G N2 Use coax cables, or low inductance wiring, to route the signal and power to and from the PCB.
PAGE 29
MCP621/1S/2/3/4/5/9 4.7.3 H-BRIDGE DRIVER Figure 4-15 shows the MCP622 dual op amp used as a H-bridge driver. The load could be a speaker or a DC motor. ½ MCP622 VIN RF RL RGT RGB VOT RF RF VDD/2 VOB ½ MCP622 FIGURE 4-15: H-Bridge Driver. This circuit automatically makes the noise gains (GN) equal, when the gains are set properly, so that the frequency responses match well (in magnitude and in phase).
PAGE 31
MCP621/1S/2/3/4/5/9 5.0 DESIGN AIDS Microchip provides the basic design aids needed for the MCP621/1S/2/3/4/5/9 family of op amps. 5.1 SPICE Macro Model The latest SPICE macro model for the MCP621/1S/2/3/4/5/9 op amps is available on the Microchip web site at www.microchip.com. This model is intended to be an initial design tool that works well in the op amp’s linear region of operation over the temperature range. See the model file for information on its capabilities.
PAGE 33
MCP621/1S/2/3/4/5/9 6.0 PACKAGING INFORMATION 6.1 Package Marking Information Example: 5-Lead SOT-23 (MCP621S) XXNN YU25 Example 6-Lead SOT-23 ( MCP623) XXNN JB25 Example: 8-Lead TDFN (2 x 3) (MCP621) AAY 129 25 8-Lead DFN (3x3) (MCP622) Example Device MCP622T-E/MF Code DABL DABL 1129 256 Note: Applies to 8-Lead 3x3 DFN Legend: XX...
PAGE 34
MCP621/1S/2/3/4/5/9 Package Marking Information (Continued) 8-Lead SOIC (150 mil) (MCP621, MCP622) Example: MCP621E SN e^^1129 3 256 NNN Example 10-Lead DFN (3x3) (MCP625) Device MCP625T-E/MF BAFA 1129 256 Code BAFA Note: Applies to 10-Lead 3x3 DFN Example: 10-Lead MSOP (MCP625) 625EUN 129256 Example 14-Lead SOIC (.
PAGE 35
MCP621/1S/2/3/4/5/9 .
PAGE 36
MCP621/1S/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22188C-page 36 © 2009-2011 Microchip Technology Inc.
PAGE 37
MCP621/1S/2/3/4/5/9 6-Lead Plastic Small Outline Transistor (CHY) [SOT-23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging b 4 N E E1 PIN 1 ID BY LASER MARK 1 2 3 e e1 D A A2 c φ L A1 L1 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 6 Pitch e 0.95 BSC Outside Lead Pitch e1 1.90 BSC Overall Height A 0.90 – Molded Package Thickness A2 0.89 – 1.45 1.
PAGE 38
MCP621/1S/2/3/4/5/9 6-Lead Plastic Small Outline Transistor (CHY) [SOT-23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22188C-page 38 © 2009-2011 Microchip Technology Inc.
PAGE 39
MCP621/1S/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2009-2011 Microchip Technology Inc.
PAGE 40
MCP621/1S/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22188C-page 40 © 2009-2011 Microchip Technology Inc.
PAGE 42
MCP621/1S/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22188C-page 42 © 2009-2011 Microchip Technology Inc.
PAGE 43
MCP621/1S/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2009-2011 Microchip Technology Inc.
PAGE 44
MCP621/1S/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22188C-page 44 © 2009-2011 Microchip Technology Inc.
PAGE 45
MCP621/1S/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2009-2011 Microchip Technology Inc.
PAGE 46
MCP621/1S/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22188C-page 46 © 2009-2011 Microchip Technology Inc.
PAGE 48
MCP621/1S/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22188C-page 48 © 2009-2011 Microchip Technology Inc.
PAGE 49
MCP621/1S/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2009-2011 Microchip Technology Inc.
PAGE 50
MCP621/1S/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22188C-page 50 © 2009-2011 Microchip Technology Inc.
PAGE 51
MCP621/1S/2/3/4/5/9 8+ & $ % 9 & .
PAGE 52
MCP621/1S/2/3/4/5/9 10-Lead Plastic Micro Small Outline Package (UN) [MSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22188C-page 52 © 2009-2011 Microchip Technology Inc.
PAGE 53
MCP621/1S/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2009-2011 Microchip Technology Inc.
PAGE 54
MCP621/1S/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22188C-page 54 © 2009-2011 Microchip Technology Inc.
PAGE 56
MCP621/1S/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22188C-page 56 © 2009-2011 Microchip Technology Inc.
PAGE 57
MCP621/1S/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2009-2011 Microchip Technology Inc.
PAGE 58
MCP621/1S/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22188C-page 58 © 2009-2011 Microchip Technology Inc.
PAGE 59
MCP621/1S/2/3/4/5/9 8; < " # $ % & ' =*=*+,4 / 0 <" .
PAGE 60
MCP621/1S/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22188C-page 60 © 2009-2011 Microchip Technology Inc.
PAGE 61
MCP621/1S/2/3/4/5/9 APPENDIX A: REVISION HISTORY Revision C (August 2011) The following is the list of modifications: 1. 2. 3. 4. Added the MCP621S and MCP623 amplifiers to the product family and the related information throughout the document. Added the 2x3 TDFN (8L) package option for MCP621, SOT-23 (5L) package for MCP621S and SOT-23 (6L) package option for MCP623 and the related information throughout the document. Updated Section 6.0 “Packaging Information” with markings for the new additions.
PAGE 63
MCP621/1S/2/3/4/5/9 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO.
PAGE 65
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 66
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