Datasheet
Table Of Contents
- 1.0 Electrical Characteristics
- 2.0 Typical Performance Curves
- FIGURE 2-1: Input Offset Voltage at VDD = 5.5V.
- FIGURE 2-2: Input Offset Voltage at VDD = 2.3V.
- FIGURE 2-3: Input Bias Current at VDD = 5.5V.
- FIGURE 2-4: Input Offset Voltage Drift at VDD = 5.5V.
- FIGURE 2-5: Input Offset Voltage Drift at VDD = 2.3V.
- FIGURE 2-6: Input Offset Current at VDD = 5.5V.
- FIGURE 2-7: Input Offset Voltage vs. Ambient Temperature.
- FIGURE 2-8: Quiescent Current vs. Ambient Temperature.
- FIGURE 2-9: Maximum Output Voltage Swing vs. Ambient Temperature at RL = 5 kW.
- FIGURE 2-10: Input Bias, Offset Currents vs. Ambient Temperature.
- FIGURE 2-11: CMRR, PSRR vs. Ambient Temperature.
- FIGURE 2-12: Maximum Output Voltage Swing vs. Ambient Temperature at RL = 25 kW.
- FIGURE 2-13: Output Short Circuit Current vs. Ambient Temperature.
- FIGURE 2-14: Slew Rate vs. Ambient Temperature.
- FIGURE 2-15: Input Bias, Offset Currents vs. Common Mode Input Voltage.
- FIGURE 2-16: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature.
- FIGURE 2-17: Input Offset Voltage vs. Common Mode Input Voltage.
- FIGURE 2-18: Input Offset Voltage vs. Output Voltage.
- FIGURE 2-19: Quiescent Current vs. Power Supply Voltage.
- FIGURE 2-20: DC Open-Loop Gain vs. Load Resistance.
- FIGURE 2-21: Gain-Bandwidth Product, Phase Margin vs. Load Resistance.
- FIGURE 2-22: Output Voltage Headroom vs. Output Current Magnitude.
- FIGURE 2-23: DC Open-Loop Gain vs. Power Supply Voltage.
- FIGURE 2-24: Channel-to-Channel Separation vs. Frequency (MCP617 and MCP619 only).
- FIGURE 2-25: Open-Loop Gain, Phase vs. Frequency.
- FIGURE 2-26: Input Noise Voltage, Current Densities vs. Frequency.
- FIGURE 2-27: Small-Signal, Non-Inverting Pulse Response.
- FIGURE 2-28: CMRR, PSRR vs. Frequency.
- FIGURE 2-29: Maximum Output Voltage Swing vs. Frequency.
- FIGURE 2-30: Small-Signal, Inverting Pulse Response.
- FIGURE 2-31: Large-Signal, Non-Inverting Pulse Response.
- FIGURE 2-32: Chip Select (CS) to Amplifier Output Response Time (MCP618 only).
- FIGURE 2-33: The MCP616/7/8/9 Show No Phase Reversal.
- FIGURE 2-34: Large-Signal, Inverting Pulse Response.
- FIGURE 2-35: Chip Select (CS) Internal Hysteresis (MCP618 only).
- FIGURE 2-36: Measured Input Current vs. Input Voltage (below VSS).
- 3.0 Pin Descriptions
- 4.0 Applications Information
- 5.0 Design Aids
- 6.0 Packaging Information
© 2008 Microchip Technology Inc. DS21613C-page 17
MCP616/7/8/9
4.4 Capacitive Loads
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. A unity-gain buffer (G = +1) is the most
sensitive to capacitive loads, though all gains show the
same general behavior.
When driving large capacitive loads with these op
amps (e.g., > 60 pF when G = +1), a small series
resistor at the output (R
ISO
in Figure 4-5) improves the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will be generally lower than the bandwidth
with no capacitive load.
FIGURE 4-5: Output Resistor, R
ISO
stabilizes large capacitive loads.
Figure 4-6 gives recommended R
ISO
values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (C
L
/G
N
), where G
N
is the
circuit’s noise gain. For non-inverting gains, G
N
and the
Signal Gain are equal. For inverting gains, G
N
is
1+|Signal Gain| (e.g., -1 V/V gives G
N
=+2V/V).
FIGURE 4-6: Recommended R
ISO
Values
for Capacitive Loads.
After selecting R
ISO
for your circuit, double-check the
resulting frequency response peaking and step
response overshoot. Modify R
ISO
’s value until the
response is reasonable. Bench evaluation and
simulations with the MCP616/7/8/9 SPICE macro
model are helpful.
4.5 MCP618 Chip Select (CS)
The MCP618 is a single op amp with Chip Select (CS).
When CS
is pulled high, the supply current drops to
50 nA (typical) and flows through the CS pin to V
SS
.
When this happens, the amplifier output is put into a
high-impedance state. By pulling CS
low, the amplifier
is enabled. The CS
pin has an internal 5 MΩ (typical)
pull-down resistor connected to V
SS
, so it will go low if
the CS pins is left floating. Figure 1-1 shows the output
voltage and supply current response to a CS pulse.
4.6 Supply Bypass
With this family of operational amplifiers, the power
supply pin (V
DD
for single supply) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good high-frequency performance. It may use a bulk
capacitor (i.e., 1 µF or larger) within 100 mm to provide
large, slow currents. This bulk capacitor is not required
and can be shared with other analog parts.
4.7 Unused Op Amps
An unused op amp in a quad package (MCP619)
should be configured as shown in Figure 4-7. These
circuits prevent the output from toggling and causing
crosstalk. Circuits A sets the op amp at its minimum
noise gain. The resistor divider produces any desired
reference voltage within the output voltage range of the
op amp; the op amp buffers that reference voltage.
Circuit B uses the minimum number of components
and operates as a comparator, but it may draw more
current.
FIGURE 4-7: Unused Op Amps.
V
IN
MCP61X
R
ISO
V
OUT
C
L
100
1,000
10,000
1.E-11 1.E-10 1.E-09 1.E-08
Normalized Load Capacitance; C
L
/G
N
(F)
Recommended R
ISO
()
10p 1n
100
10k
100p
1k
G
N
= +1
G
N
t +2
10n
V
DD
V
DD
¼ MCP619 (A) ¼ MCP619 (B)
R
1
R
2
V
DD
V
REF
V
REF
V
DD
R
2
R
1
R
2
+
-------------------
⋅
=