Datasheet
Table Of Contents
- 1.0 Electrical Characteristics
- 2.0 Typical Performance Curves
- FIGURE 2-1: Input Offset Voltage at VDD = 5.5V.
- FIGURE 2-2: Input Offset Voltage at VDD = 2.3V.
- FIGURE 2-3: Input Bias Current at VDD = 5.5V.
- FIGURE 2-4: Input Offset Voltage Drift at VDD = 5.5V.
- FIGURE 2-5: Input Offset Voltage Drift at VDD = 2.3V.
- FIGURE 2-6: Input Offset Current at VDD = 5.5V.
- FIGURE 2-7: Input Offset Voltage vs. Ambient Temperature.
- FIGURE 2-8: Quiescent Current vs. Ambient Temperature.
- FIGURE 2-9: Maximum Output Voltage Swing vs. Ambient Temperature at RL = 5 kW.
- FIGURE 2-10: Input Bias, Offset Currents vs. Ambient Temperature.
- FIGURE 2-11: CMRR, PSRR vs. Ambient Temperature.
- FIGURE 2-12: Maximum Output Voltage Swing vs. Ambient Temperature at RL = 25 kW.
- FIGURE 2-13: Output Short Circuit Current vs. Ambient Temperature.
- FIGURE 2-14: Slew Rate vs. Ambient Temperature.
- FIGURE 2-15: Input Bias, Offset Currents vs. Common Mode Input Voltage.
- FIGURE 2-16: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature.
- FIGURE 2-17: Input Offset Voltage vs. Common Mode Input Voltage.
- FIGURE 2-18: Input Offset Voltage vs. Output Voltage.
- FIGURE 2-19: Quiescent Current vs. Power Supply Voltage.
- FIGURE 2-20: DC Open-Loop Gain vs. Load Resistance.
- FIGURE 2-21: Gain-Bandwidth Product, Phase Margin vs. Load Resistance.
- FIGURE 2-22: Output Voltage Headroom vs. Output Current Magnitude.
- FIGURE 2-23: DC Open-Loop Gain vs. Power Supply Voltage.
- FIGURE 2-24: Channel-to-Channel Separation vs. Frequency (MCP617 and MCP619 only).
- FIGURE 2-25: Open-Loop Gain, Phase vs. Frequency.
- FIGURE 2-26: Input Noise Voltage, Current Densities vs. Frequency.
- FIGURE 2-27: Small-Signal, Non-Inverting Pulse Response.
- FIGURE 2-28: CMRR, PSRR vs. Frequency.
- FIGURE 2-29: Maximum Output Voltage Swing vs. Frequency.
- FIGURE 2-30: Small-Signal, Inverting Pulse Response.
- FIGURE 2-31: Large-Signal, Non-Inverting Pulse Response.
- FIGURE 2-32: Chip Select (CS) to Amplifier Output Response Time (MCP618 only).
- FIGURE 2-33: The MCP616/7/8/9 Show No Phase Reversal.
- FIGURE 2-34: Large-Signal, Inverting Pulse Response.
- FIGURE 2-35: Chip Select (CS) Internal Hysteresis (MCP618 only).
- FIGURE 2-36: Measured Input Current vs. Input Voltage (below VSS).
- 3.0 Pin Descriptions
- 4.0 Applications Information
- 5.0 Design Aids
- 6.0 Packaging Information
MCP616/7/8/9
DS21613C-page 16 © 2008 Microchip Technology Inc.
FIGURE 4-3: Example Circuit for
Calculating DC Offset.
To calculate the DC bias point and DC offset, convert
the circuit to its DC equivalent:
• Replace capacitors with open circuits
• Replace inductors with short circuits
• Replace AC voltage sources with short circuits
• Replace AC current sources with open circuits
• Convert DC sources and resistances into their
Thevenin equivalent form
The DC equivalent circuit for Figure 4-3 is shown in
Figure 4-4.
FIGURE 4-4: Equivalent DC Circuit.
Now calculate the nominal DC bias point with offset:
EQUATION 4-1:
Use the worst-case specs and source values to
determine the worst-case
output voltage range and
offset
for your design. Make sure the common mode
input voltage range and output voltage range are not
exceeded.
4.3 Rail-to-Rail Output
There are two specifications that describe the output
swing capability of the MCP616/7/8/9 family of op
amps. The first specification (Maximum Output Voltage
Swing) defines the absolute maximum swing that can
be achieved under the specified load conditions. For
instance, the output voltage swings to within 15 mV of
the negative rail with a 25 kΩ load tied to V
DD
/2.
Figure 2-33 shows how the output voltage is limited
when the input goes beyond the linear region of
operation.
The second specification that describes the output
swing capability of these amplifiers is the Linear Output
Voltage Range. This specification defines the
maximum output swing that can be achieved while the
amplifier still operates in its linear region. To verify
linear operation in this range, the large-signal DC
Open-Loop Gain (A
OL
) is measured at points inside the
supply rails. The measurement must meet the specified
A
OL
conditions in the specification table.
V
1
MCP61X
V
OUT
R
3
C
3
R
2
R
1
V
2
R
5
R
4
V
1
MCP61X
V
OUT
R
2
R
1
V
EQ
R
EQ
V
EQ
V
2
R
5
R
4
R
5
+
------------------
⋅=
R
EQ
R
4
|| R
5
=
V
OOS
= G
N
[V
OS
+ I
B
((R
1
||R
2
) – R
EQ
)
– I
OS
((R
1
||R
2
) + R
EQ
) / 2]
V
CM
= V
EQ
– (I
B
+ I
OS
/2) R
EQ
V
OUT
= V
EQ
(G
N
) – V
1
(G
N
– 1) + V
OOS
G
N
1R
2
R
1
⁄
+=
Where:
G
N
= op amp’s noise gain (from the
non-inverting input to the
output)
V
OOS
= circuit’s output offset voltage
V
OS
= op amp’s input offset voltage
I
B
= op amp’s input bias current
I
OS
= op amp’s input offset current
V
CM
= op amp’s coommon mode
input voltage