Datasheet
© 2008 Microchip Technology Inc. DS22041B-page 15
MCP6031/2/3/4
4.2 Rail-to-Rail Output
The output voltage range of the MCP6031/2/3/4 op
amps is V
SS
+ 10 mV (minimum) and V
DD
– 10 mV
(maximum) when R
L
=50kΩ is connected to V
DD
/2
and V
DD
= 5.5V. Refer to Figures 2-25 and 2-26 for
more information.
4.3 Output Loads and Battery Life
The MCP6031/2/3/4 op amp family has outstanding
quiescent current, which supports battery-powered
applications. There is minimal quiescent current glitch-
ing when Chip Select (CS
) is raised or lowered. This
prevents excessive current draw, and reduced battery
life, when the part is turned off or on.
Heavy resistive loads at the output can cause exces-
sive battery drain. Driving a DC voltage of 2.5V across
a 100 kΩ load resistor will cause the supply current to
increase by 25 µA, depleting the battery 28 times as
fast as I
Q
(0.9 µA, typical) alone.
High frequency signals (fast edge rate) across capaci-
tive loads will also significantly increase supply current.
For instance, a 0.1 µF capacitor at the output presents
an AC impedance of 15.9 kΩ (1/2πfC) to a 100 Hz
sinewave. It can be shown that the average power
drawn from the battery by a 5.0 V
p-p
sinewave
(1.77 V
rms
), under these conditions, is
EQUATION 4-1:
This will drain the battery about 12 times as fast as I
Q
alone.
4.4 Capacitive Loads
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. While a unity-gain buffer (G = +1) is the most
sensitive to capacitive loads, all gains show the same
general behavior.
When driving large capacitive loads with these op
amps (e.g., > 100 pF when G = +1), a small series
resistor at the output (R
ISO
in Figure 4-3) improves the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will be generally lower than the bandwidth
with no capacitance load.
FIGURE 4-3: Output resistor, R
ISO
stabilizes large capacitive loads.
Figure 4-4 gives recommended R
ISO
values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (C
L
/G
N
), where G
N
is the
circuit's noise gain. For non-inverting gains, G
N
and the
Signal Gain are equal. For inverting gains, G
N
is
1+|Signal Gain| (e.g., -1 V/V gives G
N
= +2 V/V).
FIGURE 4-4: Recommended R
ISO
values
for Capacitive Loads.
After selecting R
ISO
for your circuit, double-check the
resulting frequency response peaking and step
response overshoot. Modify R
ISO
’s value until the
response is reasonable. Bench evaluation and simula-
tions with the MCP6031/2/3/4 SPICE macro model are
very helpful.
4.5 MCP6033 Chip Select
The MCP6033 is a single op amp with Chip Select
(CS
). When CS is pulled high, the supply current drops
to 0.4 nA (typical) and flows through the CS
pin to V
SS
.
When this happens, the amplifier output is put into a
high impedance state. By pulling CS
low, the amplifier
is enabled. If the CS
pin is left floating, the amplifier will
not operate properly. Figure 1-1 shows the output
voltage and supply current response to a CS
pulse.
P
Supply
= (V
DD
- V
SS
) (I
Q
+ V
L(p-p)
f
C
L
)
= (5V)(0.9 µA + 5.0V
p-p
·
100Hz
·
0.1µF)
= 4.5 µW + 50 µW
V
IN
R
ISO
V
OUT
MCP603X
C
L
–
+
1000
10000
100000
1000000
1.E-11 1.E-10 1.E-09 1.E-08 1.E-07 1.E-06
Normalized Load Capacitance; C
L
/G
N
(F)
Recommended R
ISO
(Ω)
G
N
:
1 V/V
2 V/V
≥
5 V/V
10p 100p 1n 10n 100n 1µ
1M
100k
10k
1k