Datasheet

MCP6021/1R/2/3/4
DS21685D-page 18 © 2009 Microchip Technology Inc.
When driving large capacitive loads with these op
amps (e.g., > 60 pF when G = +1), a small series
resistor at the output (R
ISO
in Figure 4-3) improves the
feedback loop’s phase margin (stability) by making the
load resistive at higher frequencies. The bandwidth will
be generally lower than the bandwidth with no
capacitive load.
FIGURE 4-3: Output Resistor R
ISO
Stabilizes Large Capacitive Loads.
Figure 4-4 gives recommended R
ISO
values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (C
L
/G
N
), where G
N
is the
circuit’s noise gain. For non-inverting gains, G
N
and the
Signal Gain are equal. For inverting gains, G
N
is
1+|Signal Gain| (e.g., -1 V/V gives G
N
= +2 V/V).
FIGURE 4-4: Recommended R
ISO
values
for capacitive loads.
After selecting R
ISO
for your circuit, double-check the
resulting frequency response peaking and step
response overshoot. Modify R
ISO
’s value until the
response is reasonable. Evaluation on the bench and
simulations with the MCP6021/1R/2/3/4 Spice macro
model are helpful.
4.4 Gain Peaking
Figure 2-35 and Figure 2-36 use R
F
=1kΩ to avoid
(frequency response) gain peaking and (step
response) overshoot. The capacitance to ground at the
inverting input (C
G
) is the op amp’s common mode
input capacitance plus board parasitic capacitance. C
G
is in parallel with R
G
, which causes an increase in gain
at high frequencies for non-inverting gains greater than
1 V/V (unity gain). C
G
also reduces the phase margin
of the feedback loop for both non-inverting and
inverting gains.
FIGURE 4-5: Non-inverting Gain Circuit
with Parasitic Capacitance.
The largest value of R
F
in Figure 4-5 that should be
used is a function of noise gain (see G
N
in Section 4.3
“Capacitive Loads”) and C
G
. Figure 4-6 shows results
for various conditions. Other compensation techniques
may be used, but they tend to be more complicated to
the design.
FIGURE 4-6: Non-inverting gain circuit
with parasitic capacitance.
4.5 MCP6023 Chip Select (CS)
The MCP6023 is a single amplifier with chip select
(CS
). When CS is pulled high, the supply current drops
to 10 nA (typical) and flows through the CS
pin to V
SS
.
When this happens, the amplifier output is put into a
high-impedance state. By pulling C
S low, the amplifier
is enabled. The C
S pin has an internal 5 MΩ (typical)
pulldown resistor connected to V
SS
, so it will go low if
the CS
pin is left floating. Figure 1-1 and Figure 2-39
show the output voltage and supply current response to
a CS
pulse.
V
IN
MCP602X
R
ISO
V
OUT
C
L
10
100
1,000
10 100 1,000 10,000
Normalized Capacitance; C
L
/G
N
(pF)
Recommended R
ISO
(
Ω
)
G
N
≥ +1
V
IN
R
G
R
F
V
OUT
C
G
1.E+02
1.E+03
1.E+04
1.E+05
110
Noise Gain; G
N
(V/V)
Maximum R
F
(
Ω
)
G
N
> +1 V/V
100
1k
10k
100k
C
G
= 7 pF
C
G
= 20 pF
C
G
= 50 pF
C
G
= 100 pF