Datasheet

© 2007 Microchip Technology Inc. DS21314G-page 7
MCP601/1R/2/3/4
Note: Unless otherwise indicated, T
A
= +25°C, V
DD
= +2.7V to +5.5V, V
SS
= GND, V
CM
= V
DD
/2, V
OUT
≈ V
DD
/2,
V
L
= V
DD
/2, R
L
= 100 kΩ to V
L
, C
L
= 50 pF and CS is tied low.
FIGURE 2-13: Channel-to-Channel
Separation vs. Frequency.
FIGURE 2-14: Input Bias Current, Input
Offset Current vs. Ambient Temperature.
FIGURE 2-15: DC Open-Loop Gain vs.
Load Resistance.
FIGURE 2-16: CMRR, PSRR vs.
Frequency.
FIGURE 2-17: Input Bias Current, Input
Offset Current vs. Common Mode Input Voltage.
FIGURE 2-18: DC Open-Loop Gain vs.
Supply Voltage.
90
100
110
120
130
140
150
1.E+03 1.E+04 1.E+05 1.E+06
Frequency (Hz)
Channel-to-Channel
Separation (dB)
No Load
Input Referred
1k 10k 100k 1M
1
10
100
1000
25 35 45 55 65 75 85 95 105 115 125
Ambient Temperature (°C)
Input Bias and Offset
Currents (pA)
I
B
V
DD
= 5.5V
V
CM
= 4.3V
I
OS
80
90
100
110
120
1.E+02 1.E+03 1.E+04 1.E+05
Load Resistance (Ω)
DC Open-Loop Gain (dB)
V
DD
= 2.7V
V
DD
= 5.5V
100 1k 10k 100k
10
20
30
40
50
60
70
80
90
100
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06
Frequency (Hz)
CMRR, PSRR (dB)
CMRR
V
DD
= 5.0V
110010k1M
PSRR+
PSRR–
10 1k 100k
1
10
100
1000
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
Input Bias and Offset
Currents (pA)
I
B
, +85°C
V
DD
= 5.5V
max. V
CMR
≥ 4.3V
I
B
, +125°C
I
OS
, +85°C
I
OS
, +125°C
80
90
100
110
120
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
DC Open-Loop Gain (dB)
R
L
= 25 kΩ