Datasheet

Chapter 7.
27
The I
2
C Device Routines
There are a large number of parts available using the Inter-Integrated Circuit, or I
2
C, communications
protocol. I
2
C allows multiple devices to share a two line bus. Although communication with the devices
may occur at any speed up to 3.4 Mb/s, common rates are 100 kb/s, 400 kb/s, 1 Mb/s, 1.7 Mb/s and 3.4
Mb/s. The clock is controlled by the bus master.
To allow multiple devices to share a single bus, each device has an address. The address may be a 7 bit
or a 10 bit address, with devices supporting 7 bit addresses being far more common.
Routines for three different I
2
C devices are described.
• The MCP4726 Digital to Analog converter. The 4726 has an address range of 0x60 to 0x67 Not all
addresses are equally available.
• The MCP23008 I/O Expander. The address of this device can be set by the user in the range of 0x20 to
0x27 by external pins.
• The MB85RC16V Ferroelectric Random Access Memory (FRAM). The FRAM uses addresses 0x50
through 0x57. The multiple addresses are necessary to address all of the memory within the device.
7.1. I
2
C Device Connections
I
2
C devices are wired in parallel, with pull-up resistors on the bus. The value of the resistor is determined
by the speed desired (>2K for 5 volt systems, <20K depending on the bus capacitance[PHI1]). For higher
speeds, the designer must take care to minimize the capacitance of the bus.
Figure 7.1. I2C Wiring
The included library i2c.a provides for writing a value to the DAC, reading and writing the I/O extender,
and reading and writing the FRAM.
7.2. Using the MCP4726 DAC