Datasheet
2010 Microchip Technology Inc. DS22250A-page 23
MCP4902/4912/4922
5.0 SERIAL INTERFACE
5.1 Overview
The MCP4902/4912/4922 devices are designed to
interface directly with the Serial Peripheral Interface
(SPI) port, which is available on many microcontrollers
and supports Mode 0,0 and Mode 1,1. Commands and
data are sent to the device via the SDI pin, with data
being clocked-in on the rising edge of SCK. The
communications are unidirectional, thus the data
cannot be read out of the MCP4902/4912/4922. The
CS
pin must be held low for the duration of a write
command. The write command consists of 16 bits and
is used to configure the DAC’s control and data latches.
Register 5-1 to Register 5-3 detail the input register
that is used to configure and load the DAC
A
and DAC
B
registers for each device. Figure 5-1 to Figure 5-3
show the write command for each device.
Refer to Figure 1-1 and SPI Timing Specifications
Table for detailed input and output timing specifications
for both Mode 0,0 and Mode 1,1 operation.
5.2 Write Command
The write command is initiated by driving the CS pin
low, followed by clocking the four Configuration bits and
the 12 data bits into the SDI pin on the rising edge of
SCK. The C
S pin is then raised, causing the data to be
latched into the selected DAC’s input registers. The
MCP4902/4912/4922 utilizes a double-buffered latch
structure to allow both DAC
A
’s and DAC
B
’s outputs to
be synchronized with the LDAC
pin, if desired. Upon
the LDAC
pin achieving a low state, the values held in
the DAC’s input registers are transferred into the DAC’s
output registers. The outputs will transition to the value
and held in the DAC
X
register.
All writes to the MCP4902/4912/4922 are 16-bit words.
Any clocks past the 16th clock will be ignored. The
Most Significant 4 bits are Configuration bits. The
remaining 12 bits are data bits. No data can be
transferred into the device with CS
high. This transfer
will only occur if 16 clocks have been transferred into
the device. If the rising edge of CS
occurs prior to that,
shifting of data into the input registers will be aborted.