Datasheet

MCP4901/4911/4921
DS22248A-page 20  2010 Microchip Technology Inc.
FIGURE 4-2: Example for DNL Accuracy.
4.1.3 OFFSET ERROR
An offset error is the deviation from zero voltage output
when the digital input code is zero.
4.1.4 GAIN ERROR
A gain error is the deviation from the ideal output,
V
REF
– 1 LSB, excluding the effects of offset error.
4.2 Circuit Descriptions
4.2.1 OUTPUT AMPLIFIER
The DAC’s output is buffered with a low-power,
precision CMOS amplifier. This amplifier provides low
offset voltage and low noise. The output stage enables
the device to operate with output voltages close to the
power supply rails. Refer to Section 1.0 “Electrical
Characteristics” for the analog output voltage range
and load conditions.
In addition to resistive load driving capability, the
amplifier will also drive high capacitive loads without
oscillation. The amplifier’s strong output allows V
OUT
to
be used as a programmable voltage reference in a
system.
Selecting a gain of 2 reduces the bandwidth of the
amplifier in Multiplying mode. Refer to Section 1.0
“Electrical Characteristics” for the Multiplying mode
bandwidth for given load conditions.
4.2.1.1 Programmable Gain Block
The rail-to-rail output amplifier has two configurable
gain options: a gain of 1x (<GA
> = 1) or a gain of 2x
(<GA
> = 0). The default value is a gain of 2x
(<GA
>=0).
4.2.2 VOLTAGE REFERENCE AMPLIFIER
The input buffer amplifier for the MCP4901/4911/4921
devices provides low offset voltage and low noise. A
Configuration bit for each DAC allows the V
REF
input to
bypass the V
REF
input buffer amplifier, achieving
Buffered or Unbuffered mode. Buffered mode provides
a very high input impedance, with only minor limitations
on the input range and frequency response. Unbuf-
fered mode provides a wide input range (0V to V
DD
),
with a typical input impedance of 165 k with 7 pF.
Unbuffered mode (<BUF> = 0) is the default
configuration.
4.2.3 POWER-ON RESET CIRCUIT
The internal Power-on Reset (POR) circuit monitors the
power supply voltage (V
DD
) during device operation.
The circuit also ensures that the device powers up with
high output impedance (<SHDN> = 0, typically
500 k. The devices will continue to have a high-
impedance output until a valid write command is
received, and the LDAC
pin meets the input low thresh-
old.
If the power supply voltage is less than the POR
threshold (V
POR
= 2.0V, typical), the device will be held
in its Reset state. It will remain in that state until
V
DD
>V
POR
and a subsequent write command is
received.
Figure 4-3 shows a typical power supply transient
pulse and the duration required to cause a reset to
occur, as well as the relationship between the duration
and trip voltage. A 0.1 µF decoupling capacitor,
mounted as close as possible to the V
DD
pin, can
provide additional transient immunity.
FIGURE 4-3: Typical Transient Response.
111
110
101
100
011
010
001
000
Digital
Input
Code
Actual
Transfer
Function
Ideal Transfer
Function
Narrow Code, < 1 LSb
DAC Output
Wide Code, > 1 LSb
Transients above the
Transients below the
5V
Time
Supply Voltages
Transient Duration
V
POR
V
DD
- V
POR
T
A
=
Transient Duration (µs)
10
8
6
4
2
0
12345
V
DD
– V
POR
(V)