Datasheet

MCP4728
DS22187E-page 6 © 2010 Microchip Technology Inc.
Dynamic Performance (Note 4)
Major Code Transition
Glitch
— 45 — nV-s 1 LSB code change around major
carry (from 7FFh to 800h)
Digital Feedthrough — <10 — nV-s
Analog Crosstalk — <10 — nV-s
DAC-to-DAC Crosstalk — <10 — nV-s
Digital Interface
Output Low Voltage V
OL
— — 0.4 V I
OL
=3mA
SDA and RDY/BSY
pins
Schmitt Trigger
Low Input
Threshold Voltage
V
IL
——0.3V
DD
V V
DD
>2.7V.
SDA, SCL, LDAC
pins
——0.2V
DD
V V
DD
≤ 2.7V.
SDA, SCL, LDAC
pins
Schmitt Trigger
High Input
Threshold Voltage
V
IH
0.7V
DD
— — V SDA, SCL, LDAC pins
Input Leakage I
LI
— — ±1 µA SCL = SDA = LDAC =V
DD
,
SCL = SDA = LDAC =V
SS
Pin Capacitance C
PIN
— — 3 pF Note 4
EEPROM
EEPROM Write Time T
WRITE — 25 50 ms EEPROM write time
Data Retention — 200 — Years At +25°C, Note 3
LDAC Input
LDAC Low Time T
LDAC
210 — — ns Updates analog outputs (Note 3)
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply at V
DD
= +2.7V to 5.5V, V
SS
=0V,
R
L
=5kΩ, C
L
= 100 pF, G
X
=1, T
A
= -40°C to +125°C. Typical values are at +25°C, V
IH
=V
DD
, V
IL
=V
SS.
Parameter Symbol Min Typical Max Units Conditions
Note 1: All digital input pins (SDA, SCL, LDAC) are tied to “High”, Output pins are unloaded, code = 0 x 000.
2: The power-up ramp rate measures the rise of V
DD
over time.
3: This parameter is ensured by design and not 100% tested.
4: This parameter is ensured by characterization and not 100% tested.
5: Test code range: 100 - 4000 codes, V
REF
= V
DD
, V
DD
= 5.5V.
6: Time delay to settle to a new reference when switching from external to internal reference or vice versa.
7: This parameter is indirectly tested by Offset and Gain error testing.
8: Within 1/2 LSB of the final value when code changes from 1/4 of to 3/4 of full scale.
9: This time delay is measured from the falling edge of ACK pulse in I
2
C command to the beginning of V
OUT
.
This time delay is not included in the output settling time specification.