Datasheet

© 2010 Microchip Technology Inc. DS22187E-page 17
MCP4728
Note: Unless otherwise indicated, T
A
= -40°C to +125°C, V
DD
= +5.0V, V
SS
= 0V, R
L
= 5 kΩ, C
L
= 100 pF.
FIGURE 2-37: Entering Power Down Mode
(Code: FFFh, V
REF
= V
DD
, V
DD
= 5V,
PD1= PD0 = 1, No External Load).
FIGURE 2-38: V
OUT
Time Delay when
V
REF
changes from Internal Reference to V
DD
.
FIGURE 2-39: V
OUT
Time Delay when
V
REF
changes from V
DD
to Internal Reference.
FIGURE 2-40: Channel Cross Talk
(V
REF
= V
DD
, V
DD
= 5V).
FIGURE 2-41: Code Change Glitch
(V
REF
= External, V
DD
= 5V, No External Load),
Code Change: 800h to 7FFh.
FIGURE 2-42: Code Change Glitch
(V
REF
= Internal, V
DD
= 5V, Gain = 1, No External
Load), Code Change: 800h to 7FFh.
Time (20 µs/Div)
V
OUT
(2V/Div)
CLK
Discharging Time due to
internal pull-down resistor (500 kΩ)
Last ACK CLK pulse
V
OUT
(2V/Div)
CLK
Time (10 µs/Div)
Last ACK CLK pulse
V
OUT
(2V/Div)
CLK
Time (10 µs/Div)
Last ACK CLK pulse
Time (5 µs/Div)
V
OUT
at Channel D
V
OUT
at Channel A
(100 mV/Div)
(5V/Div)
LDAC
V
OUT
(50 mV/Div)
Time (2 µs/Div)
V
OUT
(50 mV/Div)
Time (2 µs/Div)