Datasheet

© 2011-2012 Microchip Technology Inc. DS22272C-page 43
MCP4706/4716/4726
5.0 I
2
C SERIAL INTERFACE
The MCP47X6 devices support the I
2
C serial protocol.
The MCP47X6 I
2
C’s module operates in Slave mode
(does not generate the serial clock).
5.1 Overview
This I
2
C interface is a two-wire interface. Figure 5-1
shows a typical I
2
C interface connection.
The I
2
C interface specifies different communication bit
rates. These are referred to as Standard, Fast or High-
Speed modes. The MCP47X6 supports these three
modes. The bit rates of these modes are:
• Standard mode: bit rates up to 100 kbit/s
• Fast mode: bit rates up to 400 kbit/s
• High-Speed mode (HS mode): bit rates up to
3.4 Mbit/s
A device that sends data onto the bus is defined as a
transmitter, and a device receiving data as a receiver.
The bus has to be controlled by a master device which
generates the serial clock (SCL), controls the bus
access and generates the Start and Stop conditions.
The MCP47X6 device works as slave. Both master and
slave can operate as transmitter or receiver, but the
master device determines which mode is activated.
Communication is initiated by the master
(microcontroller) which sends the Start bit, followed by
the slave address byte. The first byte transmitted is
always the slave address byte, which contains the
device code, the address bits, and the R/W
bit.
FIGURE 5-1: Typical I
2
C Interface.
The I
2
C serial protocol only defines the field types, field
lengths, timings, etc. of a frame. The frame content
defines the behavior of the device. For details on the
frame content (commands/data) refer to Section 6.0
“MCP47X6 I
2
C Commands”.
Refer to the NXP I
2
C document for more details on the
I
2
C specifications.
5.2 Signal Descriptions
The I
2
C interface uses up to two pins (signals). These
are:
• SDA (Serial Data)
• SCL (Serial Clock)
5.2.1 SERIAL DATA (SDA)
The Serial Data (SDA) signal is the data signal of the
device. The value on this pin is latched on the rising
edge of the SCL signal when the signal is an input.
With the exception of the Start and Stop conditions, the
high or low state of the SDA pin can only change when
the clock signal on the SCL pin is low. During the high
period of the clock, the SDA pin’s value (high or low)
must be stable. Changes in the SDA pin’s value while
the SCL pin is High will be interpreted as a Start or a
Stop condition.
5.2.2 SERIAL CLOCK (SCL)
The Serial Clock (SCL) signal is the clock signal of the
device. The rising edge of the SCL signal latches the
value on the SDA pin.
The MCP47X6 will not stretch the clock signal (SCL)
since memory read access occurs fast enough.
Depending on the clock rate mode, the interface will
display different characteristics.
SCL
SCL
MCP4XXX
SDA
SDA
Host
Controller
Typical I
2
C™ Interface Connections