Datasheet

MCP4706/4716/4726
DS22272C-page 36 © 2011-2012 Microchip Technology Inc.
4.2 DAC’s (Resistor Ladder)
Reference Voltage
The device can be configured to use one of three
voltage sources for the resistor ladder’s reference
voltage (V
RL
) (see Figure 4-2). These are:
1. V
DD
pin voltage
2. V
REF
pin voltage internally buffered
3. V
REF
pin voltage unbuffered
The selection of the voltage is specified with the volatile
V
REF1
:V
REF0
Configuration bits (see Table 4-4). There
are nonvolatile and volatile V
REF1
:V
REF0
Configuration
bits. On a POR/BOR event, the state of the nonvolatile
V
REF1
:V
REF0
Configuration bits are latched into the
volatile V
REF1
:V
REF0
Configuration bits.
When the user selects the V
DD
as reference, the V
REF
pin voltage is not connected to the resistor ladder.
If the V
REF
pin is selected, then select between the
Buffered or Unbuffered mode.
In Unbuffered mode, the V
REF
pin voltage may be from
V
SS
to V
DD
.
In Buffered mode, the V
REF
pin voltage may be from
0.01V to V
DD
-0.04V. The input buffer (amplifier) pro-
vides low offset voltage, low noise, and a very high
input impedance, with only minor limitations on the
input range and frequency response.
FIGURE 4-2: Resistor Ladder Reference
Voltage Selection Block Diagram.
4.3 Resistor Ladder
The resistor ladder is a digital potentiometer with the B
Terminal internally grounded and the A terminal
connected to the selected reference voltage (see
Figure 4-3). The volatile DAC register controls the
wiper position. The wiper voltage (V
W
) is proportional to
the DAC register value divided by the number of
resistor elements (R
S
) in the ladder (256, 1024, or
4096) related to the V
RL
voltage.
The resistor ladder (R
RL
) has a typical impedance of
approximately 210 kΩ. This resistor ladder resistance
(R
RL
) may vary from device to device up to ±20%.
Since this is a voltage divider configuration, the actual
R
RL
resistance does not effect the output given a fixed
voltage at V
RL
.
If the unbuffered V
REF
pin is used as the V
RL
voltage
source, this voltage source should have a low output
impedance.
When the DAC is powered down, the resistor ladder is
disconnected from the selected reference voltage.
FIGURE 4-3: Resistor Ladder.
Note: In Unbuffered mode, the voltage source
should have a low output impedance. If
the voltage source has a high output
impedance, then the voltage on the
V
REF
’s pin would be lower than expected.
The resistor ladder has a typical
impedance of 210 kΩ and a typical
capacitance of 29 pF.
Note: Any variation or noises on the reference
source can directly affect the DAC output.
The reference voltage needs to be as
clean as possible for accurate DAC
performance.
V
RL
V
DD
Buffer
Reference
V
REF1
:V
REF0
Selection
V
REF
Note: The maximum wiper position is 2
n
- 1,
while the number of resistors in the
resistor ladder is 2
n
. This means that
when the DAC register is at full scale,
there is one resistor element (R
S
)
between the wiper and the V
RL
voltage.
R
S(2
n
)
R
S(2
n
- 1)
R
S(2
n
- 2)
R
S(1)
2
n
- 1
2
n
- 2
1
0
R
RL
V
RL
V
W
DAC
Register
V
W
= * V
RL
DAC Register Value
# Resistors in Resistor Ladder
Where:
# Resistors in Resistor Ladder = 256 (MCP4706)
1024 (MCP4716)
4096 (MCP4726)
PD1:PD0