Datasheet

MCP4706/4716/4726
DS22272C-page 34 © 2011-2012 Microchip Technology Inc.
3.1 Analog Output Voltage Pin (V
OUT
)
V
OUT
is the DAC analog output pin. The DAC output
has an output amplifier. V
OUT
can swing from
approximately 0V to approximately V
DD
. The full-scale
range of the DAC output is from V
SS
to G * V
RL
, where
G is the gain selection option (1x or 2x).
In Normal mode, the DC impedance of the output pin is
about 1Ω. In Power-Down mode, the output pin is
internally connected to a known pull-down resistor of
1kΩ, 125 kΩ, or 640 kΩ. The power-down selection
bits settings are shown in Table 4-2.
3.2 Positive Power Supply Input (V
DD
)
V
DD
is the positive supply voltage input pin. The input
supply voltage is relative to V
SS
.
The power supply at the V
DD
pin should be as clean as
possible for a good DAC performance. It is
recommended to use an appropriate bypass capacitor
of about 0.1 µF (ceramic) to ground. An additional
10 µF capacitor (tantalum) in parallel is also
recommended to further attenuate high-frequency
noise present in application boards.
3.3 Ground (V
SS
)
The V
SS
pin is the device ground reference.
The user must connect the V
SS
pin to a ground plane
through a low-impedance connection. If an analog
ground path is available in the application Printed
Circuit Board (PCB), it is highly recommended that the
V
SS
pin be tied to the analog ground path or isolated
within an analog ground plane of the circuit board.
3.4 Serial Data Pin (SDA)
SDA is the serial data pin of the I
2
C interface. The SDA
pin is used to write or read the DAC registers and Con-
figuration bits. The SDA pin is an open-drain N-channel
driver. Therefore, it needs a pull-up resistor from the
V
DD
line to the SDA pin. Except for Start and Stop
conditions, the data on the SDA pin must be stable
during the high period of the clock. The high or low
state of the SDA pin can only change when the clock
signal on the SCL pin is low. Refer to Section 5.0 “I
2
C
Serial Interface” for more details of I
2
C serial interface
communication.
3.5 Serial Clock Pin (SCL)
SCL is the serial clock pin of the I
2
C interface. The
MCP47X6 devices act only as a slave and the SCL pin
accepts only external serial clocks. The input data from
the master device is shifted into the SDA pin on the
rising edges of the SCL clock and output from the
device occurs at the falling edges of the SCL clock. The
SCL pin is an open-drain N-channel driver. Therefore,
it needs a pull-up resistor from the V
DD
line to the SCL
pin. Refer to Section 5.0 “I
2
C Serial Interface” for
more details about I
2
C serial interface communication.
3.6 Voltage Reference Pin (V
REF
)
This pin is used for the external voltage reference input.
The user can select V
DD
voltage or the V
REF
pin
voltage as the reference resistor ladder’s voltage
reference.
When the V
REF
pin signal is selected, there is an option
for this voltage to be buffered or unbuffered. This is
offered in cases where the reference voltage does not
have the current capability not to drop its voltage when
connected to the internal resistor ladder circuit.
When the V
DD
is selected as reference voltage, this pin
is disconnected from the internal circuit.
See Section 4.2 “DAC’s (Resistor Ladder)
Reference Voltage” and Tabl e 4-4 for more details on
the Configuration bits.
3.7 Exposed Pad (EP)
This pad is conductively connected to the device's
substrate. This pad should be tied to the same potential
as the V
SS
pin (or left unconnected). This pad could be
used to assist as a heat sink for the device when
connected to a PCB heat sink.