Datasheet

MCP4706/4716/4726
DS22272C-page 46 © 2011-2012 Microchip Technology Inc.
5.3.4 SLOPE CONTROL
The MCP47X6 implements slope control on the SDA
output.
As the device transitions from HS mode to FS mode,
the slope control parameter will change from the HS
specification to the FS specification.
For Fast (FS) and High-Speed (HS) modes, the device
has a spike suppression and a Schmidt Trigger at SDA
and SCL inputs.
5.3.5 DEVICE ADDRESSING
The address byte is the first byte received following the
Start condition from the master device. The
MCP47X6’s slave address consists of a 4-bit fixed code
(‘1100’) and a 3-bit code that is user specified when the
device is ordered. This allows up to eight MCP47X6
devices on a single I
2
C bus.
Figure 5-9 shows the I
2
C slave address byte format,
which contains the seven address bits and a read/write
(R/W) bit. Table 5-2 shows the eight I
2
C slave address
options and their respective device order code.
FIGURE 5-9: Slave Address Bits in the
I
2
C Control Byte.
Start bit
Read/Write bit
Address Byte
R/W
ACK
Acknowledge bit
Slave Address
1
1
0
0
Slave Address (7-bits)
A2
A1
A0
Note: Address Bits (A2:A0) specified at time of device
order, see Table 5-2.
Fixed User Specified
TABLE 5-2: I
2
C ADDRESS/ORDER CODE
7-bit I
2
C™
Address
Device Order Code Comment
‘1100000’
MCP47x6A0-E/xx
MCP47x6A0T-E/xx Tape and Reel
‘1100001’
MCP47x6A1-E/xx
MCP47x6A1T-E/xx Tape and Reel
‘1100010’
MCP47x6A2-E/xx
MCP47x6A2T-E/xx Tape and Reel
‘1100011’
MCP47x6A3-E/xx
MCP47x6A3T-E/xx Tape and Reel
‘1100100’
MCP47x6A4-E/xx
MCP47x6A4T-E/xx Tape and Reel
‘1100101’
MCP47x6A5-E/xx
MCP47x6A5T-E/xx Tape and Reel
‘1100110’
MCP47x6A6-E/xx
MCP47x6A6T-E/xx Tape and Reel
‘1100111’
MCP47x6A7-E/xx
MCP47x6A7T-E/xx Tape and Reel
Note 1: The sample center will generally stock I
2
C
address ‘1100000’, other addresses may
be available.
2: ‘xx’ in the order code is the device
package code (CH for SOT-23 and MAY
for DFN)