Datasheet

MCP4706/4716/4726
DS22272C-page 44 © 2011-2012 Microchip Technology Inc.
5.3 I
2
C Operation
The MCP47X6’s I
2
C module is compatible with the
NXP I
2
C specification. The following lists some of the
module’s features:
• 7-bit slave addressing
• Supports three clock rate modes:
- Standard mode, clock rates up to 100 kHz
- Fast mode, clock rates up to 400 kHz
- High-speed mode (HS mode), clock rates up
to 3.4 MHz
• Support multi-master applications
• General call addressing (Reset and Wake-Up
commands)
The I
2
C 10-bit Addressing mode is not supported.
The NXP I
2
C specification only defines the field types,
field lengths, timings, etc. of a frame. The frame
content defines the behavior of the device. The frame
content for the MCP47X6 is defined in Section 6.0
“MCP47X6 I
2
C Commands”.
5.3.1 I
2
C BIT STATES AND SEQUENCE
Figure 5-8 shows the I
2
C transfer sequence. The serial
clock is generated by the master. The following
definitions are used for the bit states:
• Start bit (S)
• Data bit
• Acknowledge (A) bit (driven low) /
No Acknowledge (A
) bit (not driven low)
• Repeated Start bit (Sr)
• Stop bit (P)
5.3.1.1 Start Bit
The Start bit (see Figure 5-2) indicates the beginning of
a data transfer sequence. The Start bit is defined as the
SDA signal falling when the SCL signal is “High”.
FIGURE 5-2: Start Bit.
5.3.1.2 Data Bit
The SDA signal may change state while the SCL signal
is Low. While the SCL signal is High, the SDA signal
MUST be stable (see Figure 5-3).
FIGURE 5-3: Data Bit.
5.3.1.3 Acknowledge (A) Bit
The A bit (see Figure 5-4) is typically a response from
the receiving device to the transmitting device.
Depending on the context of the transfer sequence, the
A bit may indicate different things. Typically, the slave
device will supply an A response after the Start bit and
8 “data” bits have been received. An A bit has the SDA
signal low.
FIGURE 5-4: Acknowledge Waveform.
Not A (A) Response
The A bit has the SDA signal high. Table 5-1 shows
some of the conditions where the slave device will
issue a Not A (A).
If an error condition occurs (such as an A
instead of A),
then a Start bit must be issued to reset the command
state machine.
SDA
SCL
S
1st Bit
2nd Bit
SDA
SCL
Data Bit
1st Bit
2nd Bit
TABLE 5-1: MCP47X6 A/A RESPONSES
Event
Acknowledge
Bit
Response
Comment
General Call A
Slave Address
valid
A
Slave Address
not valid
A
Communication
during
EEPROM write
cycle
A After device has
received address
and command,
and valid
conditions for
EEPROM write
Bus Collision N/A I
2
C module
Resets, or a
“Don’t Care” if
the collision
occurs on the
Master’s “Start
bit”
A
8
D0
9
SDA
SCL