Datasheet

MCP4706/4716/4726
DS22272C-page 40 © 2011-2012 Microchip Technology Inc.
4.5 Power-Down Operation
To allow the application to conserve power when the
DAC operation is not required, three Power-Down
modes are available. The Power-Down Configuration
bits (PD1:PD0) control the power-down operation
(Figure 4-7). All Power-Down modes do the following:
• Turn off most of its internal circuits (op amp, resis-
tor ladder, ...)
• Op amp output becomes high-impedance to the
V
OUT
pin
• Disconnects resistor ladder from reference
voltage (V
RL
)
• Retains the value of the volatile DAC register and
Configuration bits, and the nonvolatile (EEPROM)
DAC register and Configuration bits
Depending on the selected Power-Down mode, the
following will occur:
•V
OUT
pin is switched to one of three resistive pull-
downs (See Table 4-2)
- 640kΩ (typical)
- 125kΩ (typical)
-1kΩ (typical)
There is a delay (T
PDE
) between the PD1:PD0 bits
changing from ‘00’ to either ‘01’, ‘10’, or ‘11’ and the op
amp no longer driving the V
OUT
output and the pull-
down resistors are sinking current.
In any of the Power-Down modes, where the V
OUT
pin
is not externally connected (sinking or sourcing
current), the power-down current will typically be 60 nA
(see Section 1.0 “Electrical Characteristics”).
Section 6.0 “MCP47X6 I
2
C Commands” describes
the I
2
C commands for writing the power-down bits. The
commands that can update the volatile PD1:PD0 bits
are:
• Write Volatile DAC Register
• Write Volatile Memory
• Write All Memory
• Write Volatile Configuration Bits
• General Call Reset
• General Call Wake-up
FIGURE 4-7: Op Amp to V
OUT
Pin Block
Diagram.
4.5.1 EXITING POWER-DOWN
When the device exits the Power-Down mode, the
following occurs:
• Disabled circuits (op amp, resistor ladder, ...) are
turned on
• Resistor ladder is connected to selected
reference voltage (V
RL
)
• Selected pull-down resistor is disconnected
•The V
OUT
output will be driven to the voltage
represented by the volatile DAC register’s value
and Configuration bits
The V
OUT
output signal will require time as these
circuits are powered up and the output voltage is driven
to the specified value as determined by the volatile
DAC register and Configuration bits.
The following events will change the PD1:PD0 bits to
‘00’ and therefore exit the Power-Down mode. These
are:
•Any I
2
C Write command for where the PD1:PD0
bits are ‘00’
•I
2
C General Call Wake-up Command
•I
2
C General Call Reset Command
(if nonvolatile PD1:PD0 bits are ‘00’)
Note: The I
2
C serial interface circuit is not
affected by the Power-Down mode. This
circuit remains active in order to receive
any command that might come from the
I
2
C master device.
TABLE 4-2: POWER-DOWN BITS AND
OUTPUT RESISTIVE LOAD
PD1 PD0 Function
00Normal operation
011kΩ resistor to ground
10125 kΩ resistor to ground
11640 kΩ resistor to ground
Note: Since the op amp and resistor ladder were
powered off (0V), the op amp’s input
voltage (V
W
) can be considered 0V. There
is a delay (T
PDD
) between the PD1:PD0
bits updated to ‘00’ and the op amp driving
the V
OUT
output. The op amp’s settling
time (from 0V) needs to be taken into
account to ensure the V
OUT
voltage
reflects the selected value.
V
OUT
PD1:PD0
Op
Amp
1kΩ
125 kΩ
640 kΩ
Gain (1x or 2x)
(Gx = 0 or 1)
V
W