Datasheet

© 2011-2012 Microchip Technology Inc. DS22272C-page 41
MCP4706/4716/4726
4.6 Device Resets
Device Resets can be grouped into two types: Resets
due to change in voltage (POR/BOR Reset), and
Resets caused by the system master (such as a
microcontroller).
After a device Reset, and when V
DD
≥ V
DD(MIN)
, the
device memory may be written or read.
4.6.1 POR/BOR RESET OPERATION
The POR and BOR trip points are at the same voltage,
and are determined if the V
DD
voltage is rising or falling
(see Figure 4-1). What occurs is different, depending if
the Reset is a POR or BOR Reset.
POR Reset (V
DD
Rising)
On a POR Reset, the nonvolatile memory values (DAC
register and Configuration bits) are latched into the
volatile memory. This configures the analog output
(V
OUT
) circuitry. A Reset delay timer also starts. During
this delay time, the I
2
C interface will not accept
commands.
BOR Reset (V
DD
Falling)
On a BOR Reset, the device is forced into a power-
down state. The volatile PD1:PD0 bits are forced to ‘11’
and all other volatile memory forced to ‘0’. The I
2
C
interface will not accept commands.
4.6.2 RESET COMMANDS
When the MCP47X6 is in the valid operating voltage,
the I
2
C General Call Reset command will force a
Reset event. This is similar to the POR Reset, except
that the Reset delay timer is not started.
In the case where the I
2
C interface bus does not seem
to be responsive, the technique shown in Section 8.9
“Software I2C Interface Reset Sequence” can be
used to force the I
2
C interface to be reset.
4.7 DAC Registers, Configuration
Bits, and Status Bits
The MCP47X6 devices have both volatile and
nonvolatile (EEPROM) memory. Figure 4-8 shows the
volatile and nonvolatile memory and their interaction
due to a POR event.
There are five Configuration bits in both the volatile and
nonvolatile memory, the DAC registers in both the
volatile and nonvolatile memory, and two volatile Status
bits. The DAC registers (volatile and nonvolatile) will be
either 12-bits (MCP4726), 10-bits (MCP4716), or 8-bits
(MCP4706) wide.
When the device is first powered up, it automatically
uploads the EEPROM memory values to the volatile
memory. The volatile memory determines the analog
output (V
OUT
) pin voltage. After the device is powered
up, the user can update the device memory.
The I
2
C interface is how this memory is read and
written. Refer to Section 5.0 “I
2
C Serial Interface”
and Section 6.0 “MCP47X6 I
2
C Commands” for
more details on the reading and writing the device’s
memory.
When the nonvolatile memory is written (using the I
2
C
Write All Memory command), the volatile memory is
written with the same values. The device starts writing
the EEPROM cell at the Acknowledge pulse of the
EEPROM Write command.
Tab le 4-3 shows the operation of the device Status bits,
Tab le 4-4 shows the operation of the device Configura-
tion bits, and Table 4-5 shows the factory default value
of a POR/BOR event for the device Configuration bits.
There are two Status bits. These are only in volatile
memory and give indication on the status of the device.
The POR bit indicates if the device V
DD
is above or
below the POR trip point. During normal operation, this
bit should be ‘1’. The RDY/BSY
bit indicates if an
EEPROM write cycle is in progress. While the
RDY/BSY
bit is low (during the EEPROM writing), all
commands are ignored, except for the Read command.
FIGURE 4-8: DAC Memory and POR Interaction.
V
REF1
DAC Register Value
(1)
N.V. Memory
Config Bits
Vol. Memory
POR Event
V
REF0
PD1 PD0 G
V
REF1
V
REF0
PD1 PD0 G
RDY/BSY POR
Status Bits
(2)
D
MAX
D
1
D
0
D
MAX
D
1
D
0
Note 1: The D
MAX
value depends on the device. For the MCP4706: D
MAX
= D
7
, MCP4716: D
MAX
= D
9
,
and the MCP4726: D
MAX
= D
11
.
2: Status bits are read-only.