Datasheet

 2008-2013 Microchip Technology Inc. DS22107B-page 61
MCP454X/456X/464X/466X
FIGURE 7-4: I
2
C Read (Last Memory Address Accessed).
FIGURE 7-5: I
2
C Random Read.
STOP bit
Control Byte
1010SA2A1A01A
Fixed
Address
Variable
Address
Read bits
P
0000 0 0 0D8A
1
Read bit
D3D7 D6 D5 D4 D2 D1 D0 A
2
Read Data bits
Note 1: Master Device is responsible for A / A
signal. If a A signal occurs, the MCP45XX/46XX will
abort this transfer and release the bus.
2: The Master Device will Not Acknowledge, and the MCP45XX/46XX will release the bus so the
Master Device can generate a Stop or Repeated Start condition.
3: The MCP45xx/46xx retains the last “Device Memory Address” that it has received. This is the
MCP45XX/46XX does not “corrupt” the “Device Memory Address” after Repeated Start or
Stop conditions.
4: The Device Memory Address pointer defaults to 00h on POR and BOR conditions.
STOP bit
Control Byte
READ Command
1010SA2A1A00 1
AD
AD
AD
AD
A1xXASr
0
1
2
3
Fixed
Address
Variable
Address
Device
Memory
Address
Command
Control Byte Read bits
P
0000 0 0 0D8A
1
Write bit
D3D7 D6 D5 D4 D2 D1 D0 A
2
1010 A2A1A01 A
Read bit
Repeated Start bit
Read Data bits
Note 1: Master Device is responsible for A / A
signal. If a A signal occurs, the MCP45XX/46XX will
abort this transfer and release the bus.
2: The Master Device will Not Acknowledge, and the MCP45XX/46XX will release the bus so the
Master Device can generate a Stop or Repeated Start condition.
3: The MCP45XX/46XX retains the last “Device Memory Address” that it has received. This is
the MCP45XX/46XX does not “corrupt” the “Device Memory Address” after Repeated Start or
Stop conditions.