Datasheet

 2008-2013 Microchip Technology Inc. DS22107B-page 15
MCP454X/456X/464X/466X
102A
(5)
T
RSCL
SCL rise time 100 kHz mode — 1000 ns Cb is specified to be from
10 to 400 pF (100 pF maxi-
mum for 3.4 MHz mode)
400 kHz mode 20 + 0.1Cb 300 ns
1.7 MHz mode 20 80 ns
1.7 MHz mode 20 160 ns After a Repeated Start con-
dition or an Acknowledge
bit
3.4 MHz mode 10 40 ns
3.4 MHz mode 10 80 ns After a Repeated Start
condition or an Acknowl-
edge bit
102B
(5)
T
RSDA
SDA rise time 100 kHz mode — 1000 ns Cb is specified to be from
10 to 400 pF (100 pF max
for 3.4 MHz mode)
400 kHz mode 20 + 0.1Cb 300 ns
1.7 MHz mode 20 160 ns
3.4 MHz mode 10 80 ns
103A
(5)
T
FSCL
SCL fall time 100 kHz mode — 300 ns Cb is specified to be from
10 to 400 pF (100 pF max
for 3.4 MHz mode)
400 kHz mode 20 + 0.1Cb 300 ns
1.7 MHz mode 20 80 ns
3.4 MHz mode 10 40 ns
103B
(5)
T
FSDA
SDA fall time 100 kHz mode — 300 ns Cb is specified to be from
10 to 400 pF (100 pF max
for 3.4 MHz mode)
400 kHz mode 20 + 0.1Cb
(4)
300 ns
1.7 MHz mode 20 160 ns
3.4 MHz mode 10 80 ns
106 T
HD:DAT
Data input hold
time
100 kHz mode 0 — ns 1.8V-5.5V, Note 6
400 kHz mode 0 — ns 2.7V-5.5V, Note 6
1.7 MHz mode 0 — ns 4.5V-5.5V, Note 6
3.4 MHz mode 0 — ns 4.5V-5.5V, Note 6
TABLE 1-2: I
2
C BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED)
I
2
C AC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40C  T
A  +125C (Extended)
Operating Voltage V
DD
range is described in AC/DC characteristics
Param.
No.
Sym Characteristic Min Max Units Conditions
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2: A fast-mode (400 kHz) I
2
C-bus device can be used in a standard-mode (100 kHz) I
2
C-bus system, but the
requirement t
SU;DAT
 250 ns must then be met. This will automatically be the case if the device does not
stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal,
it must output the next data bit to the SDA line.
T
R
max.+t
SU;DAT
= 1000 + 250 = 1250 ns (according to the standard-mode I
2
C bus specification) before
the SCL line is released.
3: The MCP46X1/MCP46X2 device must provide a data hold time to bridge the undefined part between V
IH
and V
IL
of the falling edge of the SCL signal. This specification is not a part of the I
2
C specification, but
must be tested in order to ensure that the output data will meet the setup and hold specifications for the
receiving device.
4: Use Cb in pF for the calculations.
5: Not tested.
6: A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do
not unintentionally create a Start or Stop condition.
7: Ensured by the T
AA
3.4 MHz specification test.