Datasheet

 2008-2013 Microchip Technology Inc. DS22107B-page 51
MCP454X/456X/464X/466X
6.2.6 HS MODE
The I
2
C specification requires that a high-speed mode
device must be ‘activated’ to operate in high-speed
(3.4 Mbit/s) mode. This is done by the Master sending
a special address byte following the START bit. This
byte is referred to as the high-speed Master Mode
Code (HSMMC).
The MCP45XX/46XX device does not acknowledge
this byte. However, upon receiving this command, the
device switches to HS mode. The device can now com-
municate at up to 3.4 Mbit/s on SDA and SCL lines.
The device will switch out of the HS mode on the next
STOP condition.
The master code is sent as follows:
1. START condition (S)
2. High-Speed Master Mode Code (0000 1XXX),
The XXX bits are unique to the high-speed (HS)
mode Master.
3. No Acknowledge (A
)
After switching to the High-Speed mode, the next
transferred byte is the I
2
C control byte, which specifies
the device to communicate with, and any number of
data bytes plus acknowledgements. The Master
Device can then either issue a Repeated Start bit to
address a different device (at High-Speed) or a Stop bit
to return to Fast/Standard bus speed. After the Stop bit,
any other Master Device (in a Multi-Master system) can
arbitrate for the I
2
C bus.
See Figure 6-10 for an illustration of the HS mode com-
mand sequence.
For more information on the HS mode, or other I
2
C
modes, please refer to the Phillips I
2
C specification.
6.2.6.1 Slope Control
The slope control on the SDA output is different
between the Fast/Standard Speed and the High-Speed
Clock modes of the interface.
6.2.6.2 Pulse Gobbler
The pulse gobbler on the SCL pin is automatically
adjusted to suppress spikes < 10 ns during HS mode.
FIGURE 6-10: HS Mode Sequence.
S
A
‘0 0 0 0 1 X X X’b
Sr
A
‘Slave Address’ A/A“Data”
P
S = Start bit
Sr = Repeated Start bit
A = Acknowledge bit
A = Not Acknowledge bit
R/W = Read/Write bit
R/W
P = Stop bit (Stop condition terminates HS Mode)
F/S-mode
HS-mode
HS-mode continues
F/S-mode
Sr
A
‘Slave Address’
R/W
HS Select Byte Control Byte Command/Data Byte(s)
Control Byte