Datasheet

MCP453X/455X/463X/465X
DS22096B-page 14  2008-2013 Microchip Technology Inc.
TABLE 1-2: I
2
C BUS DATA REQUIREMENTS (SLAVE MODE)
I
2
C AC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40C  T
A
 +125C (Extended)
Operating Voltage V
DD
range is described in AC/DC Characteristics
Param.
No.
Symbol Characteristic Min Max Units Conditions
100 T
HIGH
Clock high time 100 kHz mode 4000 — ns 1.8V-5.5V
400 kHz mode 600 — ns 2.7V-5.5V
1.7 MHz mode 120 ns 4.5V-5.5V
3.4 MHz mode 60 — ns 4.5V-5.5V
101 T
LOW
Clock low time 100 kHz mode 4700 — ns 1.8V-5.5V
400 kHz mode 1300 — ns 2.7V-5.5V
1.7 MHz mode 320 ns 4.5V-5.5V
3.4 MHz mode 160 — ns 4.5V-5.5V
102A
(Note 5)
T
RSCL
SCL rise time 100 kHz mode — 1000 ns Cb is specified to be from
10 to 400 pF (100 pF
maximum for 3.4 MHz
mode)
400 kHz mode 20 + 0.1Cb 300 ns
1.7 MHz mode 20 80 ns
1.7 MHz mode 20 160 ns After a Repeated Start
condition or an
Acknowledge bit
3.4 MHz mode 10 40 ns
3.4 MHz mode 10 80 ns After a Repeated Start
condition or an
Acknowledge bit
102B
(Note 5)
T
RSDA
SDA rise time 100 kHz mode — 1000 ns Cb is specified to be from
10 to 400 pF (100 pF max
for 3.4 MHz mode)
400 kHz mode 20 + 0.1Cb 300 ns
1.7 MHz mode 20 160 ns
3.4 MHz mode 10 80 ns
103A
(Note 5)
T
FSCL
SCL fall time 100 kHz mode — 300 ns Cb is specified to be from
10 to 400 pF (100 pF max
for 3.4 MHz mode)
400 kHz mode 20 + 0.1Cb 300 ns
1.7 MHz mode 20 80 ns
3.4 MHz mode 10 40 ns
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2: A fast-mode (400 kHz) I
2
C-bus device can be used in a standard-mode (100 kHz) I
2
C-bus system, but the
requirement t
SU;DAT
 250 ns must then be met. This will automatically be the case if the device does not
stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal,
it must output the next data bit to the SDA line.
T
R
max.+t
SU;DAT
= 1000 + 250 = 1250 ns (according to the standard-mode I
2
C bus specification) before
the SCL line is released.
3: Use C
b
in pF for the calculations.
4: Not tested.
5: A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do
not unintentionally create a Start or Stop condition.
6: Ensured by the T
AA
3.4 MHz specification test.