Datasheet

 2008-2013 Microchip Technology Inc. DS22096B-page 15
MCP453X/455X/463X/465X
103B
(Note 5)
T
FSDA
SDA fall time 100 kHz mode — 300 ns Cb is specified to be from
10 to 400 pF (100 pF max
for 3.4 MHz mode)
400 kHz mode 20 + 0.1Cb
(
Note 3
)
300 ns
1.7 MHz mode 20 160 ns
3.4 MHz mode 10 80 ns
106 T
HD:DAT
Data input hold
time
100 kHz mode 0 — ns 1.8V-5.5V, Note 5
400 kHz mode 0 — ns 2.7V-5.5V, Note 5
1.7 MHz mode 0 — ns 4.5V-5.5V, Note 5
3.4 MHz mode 0 — ns 4.5V-5.5V, Note 5
107 T
SU:DAT
Data input setup
time
100 kHz mode 250 — ns Note 2
400 kHz mode 100 — ns
1.7 MHz mode 10 — ns
3.4 MHz mode 10 — ns
109 T
AA
Output valid
from clock
100 kHz mode — 3450 ns Note 1
400 kHz mode — 900 ns
1.7 MHz mode — 150 ns Cb = 100 pF,
Note 1, Note 6
— 310 ns Cb = 400 pF,
Note 1, Note 4
3.4 MHz mode — 150 ns Cb = 100 pF, Note 1
110 T
BUF
Bus free time 100 kHz mode 4700 — ns Time the bus must be free
before a new transmission
can start
400 kHz mode 1300 — ns
1.7 MHz mode N.A. — ns
3.4 MHz mode N.A. — ns
T
SP
Input filter spike
suppression
(SDA and SCL)
100 kHz mode — 50 ns Philips Spec states N.A.
400 kHz mode — 50 ns
1.7 MHz mode — 10 ns Spike suppression
3.4 MHz mode — 10 ns Spike suppression
TABLE 1-2: I
2
C BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED)
I
2
C AC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40C  T
A
 +125C (Extended)
Operating Voltage V
DD
range is described in AC/DC Characteristics
Param.
No.
Symbol Characteristic Min Max Units Conditions
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2: A fast-mode (400 kHz) I
2
C-bus device can be used in a standard-mode (100 kHz) I
2
C-bus system, but the
requirement t
SU;DAT
 250 ns must then be met. This will automatically be the case if the device does not
stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal,
it must output the next data bit to the SDA line.
T
R
max.+t
SU;DAT
= 1000 + 250 = 1250 ns (according to the standard-mode I
2
C bus specification) before
the SCL line is released.
3: Use C
b
in pF for the calculations.
4: Not tested.
5: A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do
not unintentionally create a Start or Stop condition.
6: Ensured by the T
AA
3.4 MHz specification test.