Datasheet
MCP413X/415X/423X/425X
DS22060B-page 56 © 2008 Microchip Technology Inc.
7.7.2 CONTINUOUS INCREMENTS
Continuous Increments are possible only when writing
to the wiper registers.
Figure 7-7 shows a Continuous Increment sequence
for three continuous writes. The writes do not need to
be to the same volatile memory address.
When executing an continuous Increment commands,
the selected wiper will be altered from n to n+1 for each
Increment command received. The wiper value will
increment up to 100h on 8-bit devices and 80h on 7-bit
devices. After the wiper value has reached Full-Scale
(8-bit =100h, 7-bit =80h), the wiper value will not be
incremented further. If the Wiper register has a value
between 101h and 1FFh, the Increment command is
disabled.
Increment commands can be sent repeatedly without
raising CS
until a desired condition is met. The value in
the Volatile Wiper register can be read using a Read
Command.
When executing a continuous command string, The
Increment command can be followed by any other valid
command.
The wiper terminal will move after the command has
been received (8th clock).
After the wiper is incremented to the desired position,
the CS
pin should be forced to V
IH
to ensure that
unexpected transitions (on the SCK pin do not cause
the wiper setting to change). Driving the CS
pin to V
IH
should occur as soon as possible (within device
specifications) after the last desired increment occurs.
FIGURE 7-7: Continuous Increment Command - SDI and SDO States.
A
D
3
A
D
2
A
D
1
A
D
0
01XXA
D
3
A
D
2
A
D
1
A
D
0
01XXA
D
3
A
D
2
A
D
1
A
D
0
01XX
1111111*11111111*11111111*1Note 1, 2
111111
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note 3, 4
11111111111111
0 0 0 0 0 0 0 0 0 0 Note 3, 4
11111111111111111111110 0 Note 3, 4
(INCR COMMAND (n+1) ) (INCR COMMAND (n+2) )
(INCR COMMAND (n+3) )
SDI
SDO
COMMAND BYTE
COMMAND BYTE
COMMAND BYTE
Note 1: Only functions when writing the volatile wiper registers (AD3:AD0) 0h and 1h.
2: Valid Address/Command combination.
3: Invalid Address/Command combination.
4: If an Error Condition occurs (CMDERR = L), all following SDO bits will be low until the CMDERR
condition is cleared (the CS
pin is forced to the inactive state).