Datasheet

 2003 Microchip Technology Inc. DS11195C-page 11
MCP41XXX/42XXX
2.1 Parametric Test Circuits
FIGURE 2-25: Potentiometer Divider Non-
Linearity Error Test Circuit (DNL, INL).
FIGURE 2-26: Resistor Position Non-
Linearity Error Test Circuit (Rheostat operation
DNL, INL).
FIGURE 2-27: Wiper Resistance Test
Circuit.
FIGURE 2-28: Power Supply Sensitivity
Test Circuit (PSS, PSRR).
FIGURE 2-29: Gain vs. Frequency Test
Circuit.
FIGURE 2-30: Capacitance Test Circuit.
V+
A
B
W
V
MEAS
*
V+ = V
DD
1LSB = V+/256
DUT
*Assume infinite input impedance
+
-
A
B
W
DUT
I
W
*Assume infinite input impedance
V
MEAS
*
No Connection
+
-
B
DUT
W
+
-
I
SW
Rsw = 0.1V
Isw
Code = 00h
0.1V
V
SS
= 0 to V
DD
A
V+
A
B
W
DUT
V
A
V+ = V
DD
± 10%
PSRR (dB) = 20LOG
∆V
MEAS
)
(
PSS (%/%) = ∆V
DD
∆V
MEAS
V
DD
*Assume infinite input impedance
V
MEAS
*
∆V
DD
+
-
V
IN
-
+
+5V
V
OUT
2.5V DC
OFFSET
GND
A
B
DUT
W
~
V
IN
-
+
+5V
V
OUT
MCP601
2.5V DC
Offset
A
B
DUT
~