Datasheet

MCP40D17/18/19
DS22152B-page 10 © 2009 Microchip Technology Inc.
TABLE 1-2: I
2
C BUS DATA REQUIREMENTS (SLAVE MODE)
I
2
C AC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C ≤ T
A
≤ +125°C (Extended)
Operating Voltage VDD range is described in AC/DC characteristics
Parame-
ter No.
Sym Characteristic Min Max Units Conditions
100 T
HIGH
Clock high time 100 kHz mode 4000 — ns 1.8V-5.5V
400 kHz mode 600 — ns 2.7V-5.5V
101 T
LOW
Clock low time 100 kHz mode 4700 — ns
1.8V-5.5V
400 kHz mode 1300 — ns 2.7V-5.5V
102A
(5)
T
RSCL
SCL rise time 100 kHz mode — 1000 ns C
b
is specified to be from
10 to 400 pF
400 kHz mode 20 + 0.1Cb 300 ns
102B
(5)
T
RSDA
SDA rise time 100 kHz mode — 1000 ns C
b
is specified to be from
10 to 400 pF
400 kHz mode 20 + 0.1Cb 300 ns
103A
(5)
T
FSCL
SCL fall time 100 kHz mode — 300 ns C
b
is specified to be from
10 to 400 pF
400 kHz mode 20 + 0.1Cb 40 ns
103B
(5)
T
FSDA
SDA fall time 100 kHz mode — 300 ns C
b
is specified to be from
10 to 400 pF
400 kHz mode 20 + 0.1Cb
(4)
300 ns
106 T
HD:DAT Data input hold
time
100 kHz mode 0 — ns
1.8V-5.5V, Note 6
400 kHz mode 0 — ns 2.7V-5.5V, Note 6
107 T
SU:DAT Data input
setup time
100 kHz mode 250 — ns
(2)
400 kHz mode 100 — ns
109 T
AA
Output valid
from clock
100 kHz mode — 3450 ns
(1)
400 kHz mode — 900 ns
110 T
BUF
Bus free time 100 kHz mode 4700 — ns Time the bus must be free
before a new transmission
can start
400 kHz mode 1300 — ns
T
SP
Input filter spike
suppression
(SDA and SCL)
100 kHz mode — 50 ns Philips Spec states N.A.
400 kHz mode — 50 ns
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2: A fast-mode (400 kHz) I
2
C-bus device can be used in a standard-mode (100 kHz) I
2
C-bus system, but the
requirement tsu; DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not
stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal,
it must output the next data bit to the SDA line
T
R max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I
2
C bus specification) before
the SCL line is released.
3: The MCP40D18/MCP40D19 device must provide a data hold time to bridge the undefined part between
V
IH and VIL of the falling edge of the SCL signal. This specification is not a part of the I
2
C specification, but
must be tested in order to guarantee that the output data will meet the setup and hold specifications for the
receiving device.
4: Use C
b
in pF for the calculations.
5: Not Tested.
6: A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do
not unintentionally create a Start or Stop condition.