Datasheet

MCP3911

7.8 GAINCAL_CHn REGISTERS -

DIGITAL GAIN ERROR

CALIBRATION REGISTERS

REGISTERS

Name Bits Address Cof

GAINCAL_CH0 24

0x11

R/W

GAINCAL_CH1 24

0x17

R/W

R/W-0 R/W-0 R/W-0 ... R/W-0 R/W-0 R/W-0 R/W-0

GAINCAL_CHn

<23>

GAINCAL_CHn

<22>

GAINCAL_CHn

<21>

... GAINCAL_CHn

<3>

GAINCAL_CHn

<2>

GAINCAL_CHn

<1>

GAINCAL_CHn

<0>

bit 23 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 23:0 Digital gain error calibration value for the corresponding channel CHn. This register is 24-bit signed

MSB first coding with a range of -1x to +0.9999999x (from 0x80000 to 0x7FFFFF). The gain calibration

adds 1x to this register and multiplies it to the output code of the channel bit by bit, after offset calibra-

tion. The range of the gain calibration is thus from 0x to 1.9999999x (from 0x80000 to 0x7FFFFF). The

LSB corresponds to a 2

-23

increment in the multiplier.

CHn Output Code = (GAINCAL_CHn+1)*ADC CHn Output Code. This register is a Don't Care if

EN_GAINCAL=0 (Offset calibration disabled) but its value is not cleared by the EN_GAINCAL bit.