Datasheet

MCP3911

7.7 OFFCAL_CHn REGISTERS -

DIGITAL OFFSET ERROR

CALIBRATION REGISTERS

bit 2 VREFEXT Internal Voltage Reference Shutdown Control

1 = Internal Voltage Reference Disabled

0 = Internal Voltage Reference Enabled (Default)

bit 1 CLKEXT Internal Clock selection bits

1 = External clock drive by MCU on OSC1 pin (crystal oscillator disabled, no internal power

consumption) (Default)

0 = Crystal oscillator is enabled. A crystal must be placed between OSC1 and OSC2 pins.

bit 0 Not implemented, read as 0

REGISTERS

Name Bits Address Cof

OFFCAL_CH0 24 0x0E R/W

OFFCAL_CH1 24 0x14 R/W

R/W-0 R/W-0 R/W-0 ... R/W-0 R/W-0 R/W-0 R/W-0

OFFCAL_CHn

<23>

OFFCAL_CHn

<22>

OFFCAL_CHn

<21>

... OFFCAL_CHn

<3>

OFFCAL_CHn

<2>

OFFCAL_CHn

<1>

OFFCAL_CHn

<0>

bit 23 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 23:0 Digital Offset calibration value for the corresponding channel CHn. This register simply is added to the

output code of the channel bit-by-bit. This register is 24-bit two's complement MSB first coding.

CHn Output Code = OFFCAL_CHn + ADC CHn Output Code. This register is a Don't Care if

EN_OFFCAL=0 (Offset calibration disabled) but its value is not cleared by the EN_OFFCAL bit.