Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsData collecting ICsData acquisition IC - Analog front end (AFE) 24 Bit SSOP 20

MCP3911

7.5 STATUSCOM Register - Status

And Communication Register

Name Bits Address Cof

STATUSCOM 16 0x0A R/W

R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1

MODOUT<1> MODOUT<0>

— DR_HIZ DRMODE<1> DRMODE<0> DRSTATUS<1> DRSTATUS<0>

bit 15 bit 8

R/W-1 R/W-0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0

U-0

READ<1> READ<0> WRITE WIDTH<1> WIDTH<0> EN_OFFCAL EN_GAINCAL

—

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15:14 MODOUT<1:0>: Modulator Output Setting for MDAT pins

11 = Both CH0 and CH1 modulator outputs are present on MDAT1 and MDAT0 pins, both SINC fil-

ters are off, no data ready pulse is present

10 = CH1 ADC Modulator output present on MDAT1 pin, SINC filter on channel 1 is off, data ready

pulse from channel 1 is not present on DR

01 = CH0 ADC Modulator output present on MDAT0 pin, SINC filter on channel 0 is off, data ready

pulse from channel 0 is not present on DR pin

00 = No Modulator output is enabled, SINC filters are on, data readys are present on DR

pin for both

channels (DEFAULT)

bit 13 Unimplemented, read as 0

bit 12 DR_HIZ

: Data Ready Pin Inactive State Control

1 = The DR pin state is a logic high when data is NOT ready

0 = The DR

pin state is high impedance when data is NOT ready(DEFAULT)

bit 11:10 DRMODE<1:0>: Data Ready Pin (DR) mode configuration bits

11 = Both Data Ready pulses from CH0 and CH1 are output on DR pin

10 = Data Ready pulses from CH1 ADC are output on DR

pin. Data ready pulses from CH0 are not

present on the DR

pin.

01 = Data Ready pulses from CH0 ADC are output on DR

pin. Data ready pulses from CH1 are not

present on the DR

pin.

00 = Data Ready pulses from the lagging ADC between the two are output on DR

pin. The lagging

ADC depends on the PHASE register and on the OSR. (DEFAULT)

bit 9:8 DRSTATUS<1:0>: Data Ready Status

11 = ADC Channel 1 and Channel 0 data not ready (DEFAULT)

10 = ADC Channel 1 data not ready, ADC Channel 0 data ready

01 = ADC Channel 0 data not ready, ADC Channel 1 data ready

00 = ADC Channel 1 and Channel 0 data ready

bit 7:6 READ<1:0>: Address Loop Setting

11 = Address counter incremented, cycle through entire register set

10 = Address counter loops on register types (DEFAULT)

01 = Address counter loops on register groups

00 = Address not incremented, continually read single register

bit 5 WRITE: Address Loop Setting for Write mode

1 = Address counter loops on entire register map (DEFAULT)

0 = Address not incremented, continually write same single register