Datasheet

© 2012 Microchip Technology Inc. DS22286A-page 5
MCP3911
ZOUTV
REF
Output Impedance 2 — kΩ VREFEXT = 0
AI
DD
V
REF
Internal Voltage Reference
Operating Current
25 — µA VREFEXT=0, SHUT-
DOWN<1:0>=11
Voltage Reference Input
Input Capacitance — — 10 pF
V
REF
Differential Input Voltage
Range (VREF+ - VREF -)
1.1 — 1.3 V VREFEXT = 1
V
REF+
Absolute Voltage on
REFIN+ pin
V
REF-
+
1.1
—V
REF-
+ 1.3 V VREFEXT = 1
V
REF-
Absolute Voltage REFIN- pin -0.1 — +0.1 V REFIN- should be con-
nected to AGND when
VREFEXT=0
Master Clock Input
f
MCLK
Master Clock Input Frequency
Range
— 20 MHz CLKEXT = 1, (Note 6)
f
XTAL
Crystal Oscillator Operating
Frequency Range
1 — 20 MHz CLKEXT = 0, (Note 6)
AMCLK Analog Master Clock — — 16 MHz (Note 6)
Power Supply
AV
DD
Operating Voltage, Analog 2.7 — 3.6 V
DV
DD
Operating Voltage, Digital 2.7 — 3.6 V
I
DD,A
Operating Current, Analog
(Note 2)
— 1.5 2.3 mA BOOST<1:0>=00
— 1.8 2.8 mA BOOST<1:0>=01
— 2.5 3.5 mA BOOST<1:0>=10
— 4.4 6.25 mA BOOST<1:0>= 11
I
DD,D
Operating Current, Digital — 0.2 0.3 mA MCLK = 4 MHz,
proportional to MCLK
— 0.7 — mA MCLK = 16 MHz, pro-
portional to MCLK
I
DDS,A
Shutdown Current, Analog — — 1 µA AV
DD
pin only (Note 3)
I
DDS,D
Shutdown Current, Digital — — 1 µA DV
DD
pin only (Note 3)
TABLE 1-1: ANALOG SPECIFICATIONS TARGET TABLE (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply at AV
DD
= DV
DD
= 2.7V to 3.6V, MCLK =
4 MHz; PRE<1:0> = 00; OSR = 256; GAIN = 1; VREFEXT=0, CLKEXT=1, AZ_FREQ=0, DITHER<1:0>=11,
BOOST<1:0> = 10; V
CM
=0V; T
A
= -40°C to +125°C; V
IN
= 1.2 V
PP
= 424 mV
RMS
@ 50/60 Hz on both channels.
Sym Characteristic Min Typ Max Units Test Conditions
Note 1:
This specification implies that the ADC output is valid over this entire differential range and that there is no distortion or
instability across this input range. Dynamic Performance specified at -0.5 dB below the maximum signal range, V
IN
=
1.2VPP = 424 mV
RMS
, V
REF
= 1.2V @ 50/60 Hz. See terminology section for definition. This parameter is established
by characterization and not 100% tested. See performance graphs for other than default settings provided here.
2: For these operating currents the following configuration bit settings apply: SHUTDOWN<1:0>=00, RESET<1:0>=00,
VREFEXT=0, CLKEXT=0.
3: For these operating currents the following configuration bit settings apply: SHUTDOWN<1:0>=11, VREFEXT=1,
CLKEXT=1.
4: Applies to all gains. Offset and gain errors depend on PGA gain setting, see typical performance curves for typical per-
formance.
5: Outside of this range, ADC accuracy is not specified. An extended input range of +/-2 V can be applied continuously to
the part with no damage.
6: For proper operation, and for optimizing ADC accuracy, AMCLK should be limited to the maximum frequency defined in
the Table 5-2 as a function of the BOOST and PGA setting chosen. MCLK can take larger values as long as the pres-
caler settings (PRE<1:0>) limit AMCLK=MCLK/PRESCALE in the defined range in the Table 5-2.