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MCP3911

6.9 Data Ready Pin (DR)

To signify when channel data is ready for transmission,

the data ready signal is available on the Data Ready pin

(DR

) through an active-low pulse at the end of a

channel conversion.

The data ready pin outputs an active-low pulse with a

period that is equal to the DRCLK clock period, and

with a width equal to one DMCLK period.

When not active-low, this pin can either be in high-

impedance (when DR_HIZ

= 0) or in a defined logic

high state (when DR_HIZ

= 1). This is controlled

through the STATUSCOM register. This allows multiple

devices to share the same data ready pin (with a

pull-up resistor connected between DR

and DV

) in

3-phase, energy meter designs to reduce pin count. A

single device on the bus does not require a pull-up

resistor and therefore it is recommended to use

DR_HIZ

= 1 configuration for such applications.

After a data ready pulse has occurred, the ADC output

data can be read through SPI communication. Two sets

of latches at the output of the ADC prevent the

communication from outputting corrupted data (see

Section 6.10 “ADC Data Latches and Data Ready

Modes (DRMODE<1:0>)”).

The CS

pin has no effect on the DR pin, which means

even if CS

is logic high, data ready pulses will be pro-

vided (except when the configuration prevents them

from outputting data ready pulses). The DR pin can be

used as an interrupt when connected to an MCU or

DSP. While the RESET pin is logic low, the DR pin is

not active.

6.10 ADC Data Latches and Data Ready

Modes (DRMODE<1:0>)

To ensure that both channels’ ADC data is present at

the same time for SPI read, regardless of phase delay

settings for either or both channels, there are two sets

of ADC data latches in series with both the data ready

and the ‘read start’ triggers.

The first set of latches holds each output when the data

is ready and latches both outputs together when

DRMODE<1:0> = 00. When this mode is on, both

ADCs work together and produce one set of available

data after each data ready pulse (that corresponds to

the lagging ADC data ready). The second set of latches

ensures that when reading starts on an ADC output, the

corresponding data is latched so that no data

corruption can occur.

If an ADC read has started, in order to read the

following ADC output, the current reading needs to be

completed (all bits must be read from the ADC Output

Data registers).

6.10.1 DATA READY PIN (DR) CONTROL

USING DRMODE BITS

There are four modes that control the data ready

pulses and these modes are set with the

DRMODE<1:0> bits in the STATUSCOM register. For

power metering applications, DRMODE<1:0> = 00 is

recommended (Default mode).

The position of the data ready pulses vary, with respect

to this mode, to the OSR and to the PHASE settings:

• DRMODE<1:0> = 11: Both data ready pulses

from ADC Channel 0 and ADC Channel 1 are

output on the DR

pin.

• DRMODE<1:0> = 10: Data ready pulses from

ADC Channel 1 are output on the DR

pin. The

data ready pulse from ADC Channel 0 is not

present on the pin.

• DRMODE<1:0> = 01: Data ready pulses from

ADC Channel 0 are output on the DR

pin. The

data ready pulse from ADC Channel 1 is not

present on the pin.

• DRMODE<1:0> = 00 (Recommended and

Default mode): Data ready pulses from the

lagging ADC between the two are output on the

pin. The lagging ADC depends on the PHASE

ADCs are linked together so their data is latched

together when the lagging ADC output is ready.

6.10.2 DATA READY PULSES WITH

SHUTDOWN OR RESET

CONDITIONS

There will be no data ready pulses if DRMODE<1:0> =

00 when either one or both of the ADCs are in Reset or

shutdown. In Mode 0,0, a data ready pulse only hap-

pens when both ADCs are ready. Any data ready pulse

will correspond to one data on both ADCs. The two

ADCs are linked together and act as if there was only

one channel with the combined data of both ADCs.

This mode is very practical when both ADC channels’

data retrieval and processing need to be synchronized,

as in power metering applications.

Figure 6-9 represents the behavior of the data ready

pin with the different DRMODE configurations, while

shutdown or reset are applied.

Note: If DRMODE<1:0> = 11, the user will still

be able to retrieve the data ready pulse for

the ADC not in shutdown or Reset (i.e.,

only 1 ADC channel needs to be awake).