Datasheet

MCP3911
DS22286A-page 46 © 2012 Microchip Technology Inc.
6.7 Continuous Communication,
Looping on Address Sets
If the user wishes to read back either of the ADC
channels continuously, or both channels continuously,
the internal address counter of the MCP3911 can be
set to loop on specific register sets. In this case, there
is only one control byte on SDI to start the
communication. The part stays within the same loop
until CS
pin returns logic high.
This internal address counter allows the following
functionality:
• Read one ADC channel data continuously
• Read both ADC channels data continuously (both
ADC data can be independent or linked with
DRMODE settings)
• Continuously read/write the entire register map
• Continuously read/write each separate register
• Continuously read all Configuration registers
• Write all Configuration registers in one
communication (see Figure 6-8)
6.7.1 CONTINUOUS READ
The STATUSCOM register contains the loop settings
for the internal address counter (READ<1:0> bits and
WRITE bit). The internal address counter can either
stay constant (READ<1:0> = 00) and continuously
read the same byte, or it can auto-increment and loop
through the register groups defined below (READ<1:0>
= 01), register types (READ<1:0> = 10) or the entire
register map (READ<1:0> = 11).
Each ADC channel is configured independently as
either a 16-bit or 24-bit data word, depending on the
setting of the corresponding WIDTH bit in the
STATUSCOM register.
For continuous reading, in the case of WIDTH = 0
(16-bit), the lower byte of the ADC data is not accessed
and the part jumps automatically to the following
address (the user does not have to clock out the lower
byte since it becomes undefined for WIDTH = 0).
Figure 6-6 and Figure 6-7 represent a typical, continuous
read communication with the default settings
(DRMODE<1:0> = 00, READ<1:0> = 10) for both
WIDTH settings in case of the SPI Mode 0,0 (Figure 6-
6) and SPI Mode 1,1 (Figure 6-7). This configuration is
typically used for power metering applications.
Note: For continuous reading of ADC data in SPI
Mode 0,0 (see Figure 6-6), once the data
has been completely read after a data
ready, the SDO pin will take the MSB value
of the previous data at the end of the
reading (falling edge of the last SCK
clock). If SCK stays idle at logic low (by
definition of Mode 0,0), the SDO pin will be
updated at the falling edge of the next data
ready pulse (synchronously with the DR
pin falling edge with an output timing of
t
DODR
) with the new MSB of the data
corresponding to the data ready pulse.
This mechanism allows the MCP3911 to
continuously use read mode seamlessly in
SPI Mode 0,0. In SPI Mode 1,1, the SDO
stays in the last state (LSB of previous
data) after a complete reading which also
allows seamless continuous read mode.
(see Figure 6-7).