Datasheet

© 2012 Microchip Technology Inc. DS22286A-page 41
MCP3911
5.11 Crystal Oscillator
The MCP3911 includes a Pierce-type crystal oscillator
with very high stability and ensures very low tempco
and jitter for the clock generation. This oscillator can
handle up to 20 MHz crystal frequencies, provided that
proper load capacitances and quartz quality factor are
used.
For a proper start-up, the load capacitors of the crystal
should be connected between OSC1 and DGND and
between OSC2 and DGND. They should also respect
the following equation:
EQUATION 5-6:
When CLKEXT=1, the crystal oscillator is bypassed by
a digital buffer to allow direct clock input for an external
clock (see Figure 4-1).
When CLKEXT=1, it is recommended to connect
OSC2 pin to DGND directly at all times. The external
clock should not be higher than 20 MHz before pres-
caler (MCLK < 20 MHz) for proper operation.
5.12 Digital System Offset and Gain
Errors
The MCP3911 incorporates two sets of additional reg-
isters per channel, to perform system digital offset and
gain errors calibration. Each channel has its own set of
registers associated that will modify the output result of
the channel, if the calibration is enabled. The gain and
offset calibrations can be enabled or disabled through
two configuration bits (EN_OFFCAL and
EN_GAINCAL). These two bits enable or disable sys-
tem calibration on both channels at the same time.
When both calibrations are enabled, the output of the
ADC is modified as follows:
EQUATION 5-7: DIGITAL OFFSET AND GAIN ERROR CALIBRATION REGISTERS
CALCULATIONS
TABLE 5-9: PHASE VALUES WITH
MCLK = 4 MHZ, OSR = 4096
Phase Register Value
Hex Delay
(CH0 relative
to CH1)
011111111111 0x7FF + 2047 µs
011111111110 0x7FE + 2046 µs
000000000001 0x001 + 1 µs
000000000000 0x000 0 µs
111111111111 0xFFF - 1 µs
100000000001 0x801 - 2048 µs
100000000000 0x800 -2048 µs
R
M
1.6 10
6
×
1
fC•
LOAD
------------------------
⎝⎠
⎛⎞
×
2
<
Where:
f = crystal frequency in MHz
C
LOAD
= load capacitance in pF including
parasitics from the PCB
R
M
= motional resistance in ohms of
the quartz
Note: In addition to the conditions defining the
maximum MCLK input frequency range,
the AMCLK frequency should be main-
tained inferior to the maximum limits
defined in Table 5- 2 to guarantee the
accuracy of the ADCs. If these limits are
exceeded, it is recommended to either
choose a larger OSR, or a large prescaler
value, so that AMCLK can respect these
limits.
DATA_CHn post cal–()DATA_CHn pre cal–()OFFCAL_CHn+()1 GAINCAL_CHn+()×=